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target/mips: Clean up handling of CP0 register 2

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Clean up handling of CP0 register 2.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-4-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:27 +02:00
parent 30deb4605b
commit 6d27d5bd73
2 changed files with 39 additions and 32 deletions
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7
target/mips/cpu.h
View File

@ -292,6 +292,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7 #define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */ /* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0 #define CP0_REG02__ENTRYLO0 0
#define CP0_REG02__TCSTATUS 1
#define CP0_REG02__TCBIND 2
#define CP0_REG02__TCRESTART 3
#define CP0_REG02__TCHALT 4
#define CP0_REG02__TCCONTEXT 5
#define CP0_REG02__TCSCHEDULE 6
#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */ /* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0 #define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1 #define CP0_REG03__GLOBALNUM 1

64
target/mips/translate.c
View File

@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_02: case CP0_REGISTER_02:
switch (sel) { switch (sel) {
case 0: case CP0_REG02__ENTRYLO0:
{ {
TCGv_i64 tmp = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, tcg_gen_ld_i64(tmp, cpu_env,
@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
} }
register_name = "EntryLo0"; register_name = "EntryLo0";
break; break;
case 1: case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env); gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus"; register_name = "TCStatus";
break; break;
case 2: case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env); gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind"; register_name = "TCBind";
break; break;
case 3: case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env); gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart"; register_name = "TCRestart";
break; break;
case 4: case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env); gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt"; register_name = "TCHalt";
break; break;
case 5: case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env); gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext"; register_name = "TCContext";
break; break;
case 6: case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env); gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule"; register_name = "TCSchedule";
break; break;
case 7: case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env); gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack"; register_name = "TCScheFBack";
@ -7650,41 +7650,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_02: case CP0_REGISTER_02:
switch (sel) { switch (sel) {
case 0: case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg); gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0"; register_name = "EntryLo0";
break; break;
case 1: case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg); gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus"; register_name = "TCStatus";
break; break;
case 2: case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg); gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind"; register_name = "TCBind";
break; break;
case 3: case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg); gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart"; register_name = "TCRestart";
break; break;
case 4: case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg); gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt"; register_name = "TCHalt";
break; break;
case 5: case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg); gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext"; register_name = "TCContext";
break; break;
case 6: case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg); gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule"; register_name = "TCSchedule";
break; break;
case 7: case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg); gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack"; register_name = "TCScheFBack";
@ -8395,41 +8395,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_02: case CP0_REGISTER_02:
switch (sel) { switch (sel) {
case 0: case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0"; register_name = "EntryLo0";
break; break;
case 1: case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env); gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus"; register_name = "TCStatus";
break; break;
case 2: case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env); gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind"; register_name = "TCBind";
break; break;
case 3: case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env); gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart"; register_name = "TCRestart";
break; break;
case 4: case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env); gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt"; register_name = "TCHalt";
break; break;
case 5: case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env); gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext"; register_name = "TCContext";
break; break;
case 6: case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env); gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule"; register_name = "TCSchedule";
break; break;
case 7: case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env); gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack"; register_name = "TCScheFBack";
@ -9108,41 +9108,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_02: case CP0_REGISTER_02:
switch (sel) { switch (sel) {
case 0: case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg); gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0"; register_name = "EntryLo0";
break; break;
case 1: case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg); gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus"; register_name = "TCStatus";
break; break;
case 2: case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg); gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind"; register_name = "TCBind";
break; break;
case 3: case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg); gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart"; register_name = "TCRestart";
break; break;
case 4: case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg); gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt"; register_name = "TCHalt";
break; break;
case 5: case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg); gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext"; register_name = "TCContext";
break; break;
case 6: case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg); gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule"; register_name = "TCSchedule";
break; break;
case 7: case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg); gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack"; register_name = "TCScheFBack";