mirror of
https://github.com/xemu-project/xemu.git
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X86 queue 2015-06-02
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJVbgItAAoJECgHk2+YTcWmGhYP/RMNvcoOQzfRZ1xqztQlm2cp WRSnsQm2+16omGypuEGTgjr/pojlD/xRllhFMJqYPGt0ZSmwsd6AgZtU5hLnHGRb HJdq1js7GPsduR8/DPoBCAD6nA8wsrdjBt5WZkCf35WU4CaPFDTx1w35KdekdzVS 0guhSypAQdrxIULvPteJw/S6u6OA42nads2xClfvmzE3kKnedeBcLLE/GzrrkIc3 5aFjS1ndVK9rtOBldnIqq10q89c7ug60wuZi0SFqf1r4Do9cZqQgmXU7c0OiJu1G 05F0racvGaCMNp1JyH6z5pvPVjImZfu06Wz0+433hKSHvNqh25mJ4lZVGcqfHFoB Ek2+iam6xej1+I2Wbt3NOBR8K0ldDMtnVpUiXMUvT2j4AUQBc2Cs79rXBgY8Qz3P 48fI2xMlOY0TFIQTra38ZomX4Jkukhu38BRixed2/CGi1mo6N9GT5OCYBBsy2MgW o4yFmnzJD8eCopWXFXc93Pvdvrpn5/NJsmiNDFO66lxfQr+VfqzlG6eWpxQ7wXpR /JY8k21R0gHB02v7B2Kyqdj9UXmunYWS28P6LJ/z5UtCCivr/+szUTdKDOvKXt42 HrVGgpEscs0huvsUPzJRtCYYsgKIEZB7UTxOxHiAPmBOBBnB/pLiOrkoZuQIiQee KxjJWNd9wMOyx90t54AI =VKFL -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging X86 queue 2015-06-02 # gpg: Signature made Tue Jun 2 20:21:17 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: arch_init: Drop target-x86_64.conf target-i386: Register QOM properties for feature flags apic: convert ->busdev.qdev casts to C casts target-i386: Fix signedness of MSR_IA32_APICBASE_BASE pc: Ensure non-zero CPU ref count after attaching to ICC bus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
6fa6b31276
7
Makefile
7
Makefile
@ -389,13 +389,8 @@ ifneq (,$(findstring qemu-ga,$(TOOLS)))
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endif
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endif
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install-confdir:
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$(INSTALL_DIR) "$(DESTDIR)$(qemu_confdir)"
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install-sysconfig: install-datadir install-confdir
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$(INSTALL_DATA) $(SRC_PATH)/sysconfigs/target/target-x86_64.conf "$(DESTDIR)$(qemu_confdir)"
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install: all $(if $(BUILD_DOCS),install-doc) install-sysconfig \
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install: all $(if $(BUILD_DOCS),install-doc) \
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install-datadir install-localstatedir
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ifneq ($(TOOLS),)
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$(call install-prog,$(TOOLS),$(DESTDIR)$(bindir))
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@ -136,7 +136,6 @@ static struct defconfig_file {
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bool userconfig;
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} default_config_files[] = {
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{ CONFIG_QEMU_CONFDIR "/qemu.conf", true },
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{ CONFIG_QEMU_CONFDIR "/target-" TARGET_NAME ".conf", true },
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{ NULL }, /* end of list */
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};
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11
hw/i386/pc.c
11
hw/i386/pc.c
@ -1006,7 +1006,6 @@ static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
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}
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qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
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object_unref(OBJECT(cpu));
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object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
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object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
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@ -1025,7 +1024,9 @@ static const char *current_cpu_model;
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void pc_hot_add_cpu(const int64_t id, Error **errp)
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{
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DeviceState *icc_bridge;
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X86CPU *cpu;
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int64_t apic_id = x86_cpu_apic_id_from_index(id);
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Error *local_err = NULL;
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if (id < 0) {
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error_setg(errp, "Invalid CPU id: %" PRIi64, id);
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@ -1053,7 +1054,12 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
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icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
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TYPE_ICC_BRIDGE, NULL));
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pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
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cpu = pc_new_cpu(current_cpu_model, apic_id, icc_bridge, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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object_unref(OBJECT(cpu));
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}
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void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
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@ -1087,6 +1093,7 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
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error_report_err(error);
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exit(1);
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}
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object_unref(OBJECT(cpu));
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}
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/* map APIC MMIO area if CPU has APIC */
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@ -370,13 +370,14 @@ static int apic_irq_pending(APICCommonState *s)
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static void apic_update_irq(APICCommonState *s)
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{
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CPUState *cpu;
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DeviceState *dev = (DeviceState *)s;
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cpu = CPU(s->cpu);
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if (!qemu_cpu_is_self(cpu)) {
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cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
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} else if (apic_irq_pending(s) > 0) {
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cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
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} else if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
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} else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
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cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
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}
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}
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@ -549,10 +550,12 @@ static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
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static bool apic_check_pic(APICCommonState *s)
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{
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if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
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DeviceState *dev = (DeviceState *)s;
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if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
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return false;
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}
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apic_deliver_pic_intr(&s->busdev.qdev, 1);
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apic_deliver_pic_intr(dev, 1);
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return true;
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}
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@ -2841,12 +2841,126 @@ out:
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}
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}
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typedef struct BitProperty {
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uint32_t *ptr;
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uint32_t mask;
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} BitProperty;
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static void x86_cpu_get_bit_prop(Object *obj,
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struct Visitor *v,
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void *opaque,
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const char *name,
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Error **errp)
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{
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BitProperty *fp = opaque;
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bool value = (*fp->ptr & fp->mask) == fp->mask;
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visit_type_bool(v, &value, name, errp);
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}
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static void x86_cpu_set_bit_prop(Object *obj,
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struct Visitor *v,
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void *opaque,
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const char *name,
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Error **errp)
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{
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DeviceState *dev = DEVICE(obj);
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BitProperty *fp = opaque;
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Error *local_err = NULL;
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bool value;
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if (dev->realized) {
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qdev_prop_set_after_realize(dev, name, errp);
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return;
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}
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visit_type_bool(v, &value, name, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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if (value) {
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*fp->ptr |= fp->mask;
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} else {
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*fp->ptr &= ~fp->mask;
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}
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}
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static void x86_cpu_release_bit_prop(Object *obj, const char *name,
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void *opaque)
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{
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BitProperty *prop = opaque;
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g_free(prop);
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}
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/* Register a boolean property to get/set a single bit in a uint32_t field.
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*
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* The same property name can be registered multiple times to make it affect
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* multiple bits in the same FeatureWord. In that case, the getter will return
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* true only if all bits are set.
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*/
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static void x86_cpu_register_bit_prop(X86CPU *cpu,
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const char *prop_name,
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uint32_t *field,
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int bitnr)
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{
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BitProperty *fp;
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ObjectProperty *op;
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uint32_t mask = (1UL << bitnr);
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op = object_property_find(OBJECT(cpu), prop_name, NULL);
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if (op) {
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fp = op->opaque;
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assert(fp->ptr == field);
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fp->mask |= mask;
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} else {
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fp = g_new0(BitProperty, 1);
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fp->ptr = field;
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fp->mask = mask;
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object_property_add(OBJECT(cpu), prop_name, "bool",
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x86_cpu_get_bit_prop,
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x86_cpu_set_bit_prop,
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x86_cpu_release_bit_prop, fp, &error_abort);
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}
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}
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static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
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FeatureWord w,
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int bitnr)
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{
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Object *obj = OBJECT(cpu);
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int i;
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char **names;
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FeatureWordInfo *fi = &feature_word_info[w];
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if (!fi->feat_names) {
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return;
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}
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if (!fi->feat_names[bitnr]) {
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return;
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}
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names = g_strsplit(fi->feat_names[bitnr], "|", 0);
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feat2prop(names[0]);
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x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
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for (i = 1; names[i]; i++) {
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feat2prop(names[i]);
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object_property_add_alias(obj, names[i], obj, g_strdup(names[0]),
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&error_abort);
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}
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g_strfreev(names);
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}
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static void x86_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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X86CPU *cpu = X86_CPU(obj);
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X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
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CPUX86State *env = &cpu->env;
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FeatureWord w;
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static int inited;
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cs->env_ptr = env;
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@ -2887,6 +3001,14 @@ static void x86_cpu_initfn(Object *obj)
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cpu->apic_id = -1;
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#endif
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for (w = 0; w < FEATURE_WORDS; w++) {
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int bitnr;
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for (bitnr = 0; bitnr < 32; bitnr++) {
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x86_cpu_register_feature_bit_props(cpu, w, bitnr);
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}
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}
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x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
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/* init various static tables used in TCG mode */
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@ -305,7 +305,7 @@
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#define MSR_IA32_APICBASE 0x1b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_TSC_ADJUST 0x0000003b
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#define MSR_IA32_TSCDEADLINE 0x6e0
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