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target-arm: Move get/set_r13_banked() to op_helper.c
Move get/set_r13_banked() from helper.c to op_helper.c. This will let us add exception-raising code to them, and also puts them in the same file as get/set_user_reg(), which makes some conceptual sense. (The original reason for the helper.c/op_helper.c split was that only op_helper.c had access to the CPU env pointer; this distinction has not been true for a long time, though, and so the split is now rather arbitrary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -5365,21 +5365,6 @@ void switch_mode(CPUARMState *env, int mode)
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}
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}
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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cpu_abort(CPU(cpu), "banked r13 write\n");
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}
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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cpu_abort(CPU(cpu), "banked r13 read\n");
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return 0;
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}
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uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
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uint32_t cur_el, bool secure)
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{
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@ -7762,24 +7747,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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return phys_addr;
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}
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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env->regs[13] = val;
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} else {
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env->banked_r13[bank_number(mode)] = val;
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}
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}
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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return env->regs[13];
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} else {
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return env->banked_r13[bank_number(mode)];
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}
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}
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uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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@ -457,6 +457,43 @@ void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
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}
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}
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#if defined(CONFIG_USER_ONLY)
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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cpu_abort(CPU(cpu), "banked r13 write\n");
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}
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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cpu_abort(CPU(cpu), "banked r13 read\n");
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return 0;
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}
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#else
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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env->regs[13] = val;
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} else {
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env->banked_r13[bank_number(mode)] = val;
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}
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}
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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return env->regs[13];
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} else {
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return env->banked_r13[bank_number(mode)];
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}
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}
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#endif
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void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
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uint32_t isread)
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{
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