mirror of
https://github.com/xemu-project/xemu.git
synced 2024-11-24 03:59:52 +00:00
hw/intc/arm_gic: Drop running_irq and last_active arrays
The running_irq and last_active arrays represent state which doesn't exist in a real hardware GIC. The only thing we use them for is updating the running priority when an interrupt is completed, but in fact we can use the active-priority registers to do this. The running priority is always the priority corresponding to the lowest set bit in the active priority registers, because only one interrupt at any particular priority can be active at once. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1438089748-5528-5-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
51fd06e0ee
commit
72889c8a80
@ -245,15 +245,72 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
|
||||
return GIC_GET_PRIORITY(irq, cpu) & mask;
|
||||
}
|
||||
|
||||
static void gic_set_running_irq(GICState *s, int cpu, int irq)
|
||||
static void gic_activate_irq(GICState *s, int cpu, int irq)
|
||||
{
|
||||
s->running_irq[cpu] = irq;
|
||||
if (irq == 1023) {
|
||||
s->running_priority[cpu] = 0x100;
|
||||
/* Set the appropriate Active Priority Register bit for this IRQ,
|
||||
* and update the running priority.
|
||||
*/
|
||||
int prio = gic_get_group_priority(s, cpu, irq);
|
||||
int preemption_level = prio >> (GIC_MIN_BPR + 1);
|
||||
int regno = preemption_level / 32;
|
||||
int bitno = preemption_level % 32;
|
||||
|
||||
if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
|
||||
s->nsapr[regno][cpu] &= (1 << bitno);
|
||||
} else {
|
||||
s->running_priority[cpu] = gic_get_group_priority(s, cpu, irq);
|
||||
s->apr[regno][cpu] &= (1 << bitno);
|
||||
}
|
||||
gic_update(s);
|
||||
|
||||
s->running_priority[cpu] = prio;
|
||||
}
|
||||
|
||||
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
|
||||
{
|
||||
/* Recalculate the current running priority for this CPU based
|
||||
* on the set bits in the Active Priority Registers.
|
||||
*/
|
||||
int i;
|
||||
for (i = 0; i < GIC_NR_APRS; i++) {
|
||||
uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu];
|
||||
if (!apr) {
|
||||
continue;
|
||||
}
|
||||
return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
|
||||
}
|
||||
return 0x100;
|
||||
}
|
||||
|
||||
static void gic_drop_prio(GICState *s, int cpu, int group)
|
||||
{
|
||||
/* Drop the priority of the currently active interrupt in the
|
||||
* specified group.
|
||||
*
|
||||
* Note that we can guarantee (because of the requirement to nest
|
||||
* GICC_IAR reads [which activate an interrupt and raise priority]
|
||||
* with GICC_EOIR writes [which drop the priority for the interrupt])
|
||||
* that the interrupt we're being called for is the highest priority
|
||||
* active interrupt, meaning that it has the lowest set bit in the
|
||||
* APR registers.
|
||||
*
|
||||
* If the guest does not honour the ordering constraints then the
|
||||
* behaviour of the GIC is UNPREDICTABLE, which for us means that
|
||||
* the values of the APR registers might become incorrect and the
|
||||
* running priority will be wrong, so interrupts that should preempt
|
||||
* might not do so, and interrupts that should not preempt might do so.
|
||||
*/
|
||||
int i;
|
||||
|
||||
for (i = 0; i < GIC_NR_APRS; i++) {
|
||||
uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
|
||||
if (!*papr) {
|
||||
continue;
|
||||
}
|
||||
/* Clear lowest set bit */
|
||||
*papr &= *papr - 1;
|
||||
break;
|
||||
}
|
||||
|
||||
s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
|
||||
}
|
||||
|
||||
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
|
||||
@ -276,7 +333,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
|
||||
DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq);
|
||||
return 1023;
|
||||
}
|
||||
s->last_active[irq][cpu] = s->running_irq[cpu];
|
||||
|
||||
if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
|
||||
/* Clear pending flags for both level and edge triggered interrupts.
|
||||
@ -307,7 +363,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
|
||||
}
|
||||
}
|
||||
|
||||
gic_set_running_irq(s, cpu, irq);
|
||||
gic_activate_irq(s, cpu, irq);
|
||||
gic_update(s);
|
||||
DPRINTF("ACK %d\n", irq);
|
||||
return ret;
|
||||
}
|
||||
@ -437,8 +494,9 @@ static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
|
||||
|
||||
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
|
||||
{
|
||||
int update = 0;
|
||||
int cm = 1 << cpu;
|
||||
int group;
|
||||
|
||||
DPRINTF("EOI %d\n", irq);
|
||||
if (irq >= s->num_irq) {
|
||||
/* This handles two cases:
|
||||
@ -451,8 +509,9 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
|
||||
*/
|
||||
return;
|
||||
}
|
||||
if (s->running_irq[cpu] == 1023)
|
||||
if (s->running_priority[cpu] == 0x100) {
|
||||
return; /* No active IRQ. */
|
||||
}
|
||||
|
||||
if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
|
||||
/* Mark level triggered interrupts as pending if they are still
|
||||
@ -461,11 +520,12 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
|
||||
&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
|
||||
DPRINTF("Set %d pending mask %x\n", irq, cm);
|
||||
GIC_SET_PENDING(irq, cm);
|
||||
update = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (s->security_extn && !attrs.secure && !GIC_TEST_GROUP(irq, cm)) {
|
||||
group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
|
||||
|
||||
if (s->security_extn && !attrs.secure && !group) {
|
||||
DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
|
||||
return;
|
||||
}
|
||||
@ -475,23 +535,8 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
|
||||
* i.e. go ahead and complete the irq anyway.
|
||||
*/
|
||||
|
||||
if (irq != s->running_irq[cpu]) {
|
||||
/* Complete an IRQ that is not currently running. */
|
||||
int tmp = s->running_irq[cpu];
|
||||
while (s->last_active[tmp][cpu] != 1023) {
|
||||
if (s->last_active[tmp][cpu] == irq) {
|
||||
s->last_active[tmp][cpu] = s->last_active[irq][cpu];
|
||||
break;
|
||||
}
|
||||
tmp = s->last_active[tmp][cpu];
|
||||
}
|
||||
if (update) {
|
||||
gic_update(s);
|
||||
}
|
||||
} else {
|
||||
/* Complete the current running IRQ. */
|
||||
gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
|
||||
}
|
||||
gic_drop_prio(s, cpu, group);
|
||||
gic_update(s);
|
||||
}
|
||||
|
||||
static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
|
||||
|
||||
@ -59,8 +59,8 @@ static const VMStateDescription vmstate_gic_irq_state = {
|
||||
|
||||
static const VMStateDescription vmstate_gic = {
|
||||
.name = "arm_gic",
|
||||
.version_id = 11,
|
||||
.minimum_version_id = 11,
|
||||
.version_id = 12,
|
||||
.minimum_version_id = 12,
|
||||
.pre_save = gic_pre_save,
|
||||
.post_load = gic_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
@ -71,10 +71,8 @@ static const VMStateDescription vmstate_gic = {
|
||||
VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
|
||||
VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
|
||||
VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
|
||||
VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
|
||||
VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
|
||||
VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
|
||||
VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
|
||||
VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
|
||||
VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
|
||||
VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
|
||||
@ -174,7 +172,6 @@ static void arm_gic_common_reset(DeviceState *dev)
|
||||
s->priority_mask[i] = 0;
|
||||
}
|
||||
s->current_pending[i] = 1023;
|
||||
s->running_irq[i] = 1023;
|
||||
s->running_priority[i] = 0x100;
|
||||
s->cpu_ctlr[i] = 0;
|
||||
s->bpr[i] = GIC_MIN_BPR;
|
||||
|
||||
@ -68,7 +68,6 @@ typedef struct GICState {
|
||||
uint8_t irq_target[GIC_MAXIRQ];
|
||||
uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
|
||||
uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
|
||||
uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
|
||||
/* For each SGI on the target CPU, we store 8 bits
|
||||
* indicating which source CPUs have made this SGI
|
||||
* pending on the target CPU. These correspond to
|
||||
@ -78,7 +77,6 @@ typedef struct GICState {
|
||||
uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
|
||||
|
||||
uint16_t priority_mask[GIC_NCPU];
|
||||
uint16_t running_irq[GIC_NCPU];
|
||||
uint16_t running_priority[GIC_NCPU];
|
||||
uint16_t current_pending[GIC_NCPU];
|
||||
|
||||
@ -96,14 +94,6 @@ typedef struct GICState {
|
||||
* If an interrupt for preemption level X is active, then
|
||||
* APRn[X mod 32] == 0b1, where n = X / 32
|
||||
* otherwise the bit is clear.
|
||||
*
|
||||
* TODO: rewrite the interrupt acknowlege/complete routines to use
|
||||
* the APR registers to track the necessary information to update
|
||||
* s->running_priority[] on interrupt completion (ie completely remove
|
||||
* last_active[][] and running_irq[]). This will be necessary if we ever
|
||||
* want to support TCG<->KVM migration, or TCG guests which can
|
||||
* do power management involving powering down and restarting
|
||||
* the GIC.
|
||||
*/
|
||||
uint32_t apr[GIC_NR_APRS][GIC_NCPU];
|
||||
uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user