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ppc patch queue 2018-11-08
Here's another patch of accumulated ppc patches for qemu-3.1. Highlights are: * Support for nested HV KVM on POWER9 hosts * Remove Alex Graf as ppc maintainer * Emulation of external PID instructions -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlvkKKMACgkQbDjKyiDZ s5KO3Q/+Ise1jJuTzL1/ga8cTF8wil/C9hJMQKXFtcVDJuCNL+RtIUGS1/zsGB/O 4Zemp0KxdCOoJKEvtndJSP/2b4++35edXO/u2vSLrtCGnidEnGcgaIBHve3huOPf zVtnbvRcNOHUbYC4GwsihqbxFI6hdKmMsR0THjpriCzTQPBjkqQyaK/oHyUFTS/F vNiWGxvJjOaFrszt0TSdEFwIcjtIib99zueAkIpIQIVpy65mM9VkL83CmV9ATfxP G9ZVWjCNzVSjGGKKArLCOnajaqdpGH8hKPqfTHjBOIapgCXJsDI1/+i1Kh2/H+Fa BaWxpR9lkMUQZniOn1oFGNmAKmLZiqAPRt5IeUruzKigfwlnG4gcv8LoZSOcxk/V Kh/Odra3dWIgfCcEr8qYp7tJ6+izAxb/iOOM2eHPN2eAejcO8tReyKwLgCxCX6jm obBlBocoRY8pEpgXjusgGWTiBwiJkPfx9cjlkvY+hHYeXpUkJiCkTURAWHM8+Nuh 9ZSqtoKuqSLIpsNi+oLT4qT4I0L14koRGu+ARVe5IpyJO36Ru3PtmnQKxeBm+559 sfgZiZ6fpJN2nOgKNPcP+kkxVm+W8hj8Uk2VGnl9ZLA7CPVSJaZRwQt0Gths41CC tmWcoQeYTCdElkjNQchs9+eoMRPIvs6x+TjgdrhaBg30d3O9kng= =NIAZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20181108' into staging ppc patch queue 2018-11-08 Here's another patch of accumulated ppc patches for qemu-3.1. Highlights are: * Support for nested HV KVM on POWER9 hosts * Remove Alex Graf as ppc maintainer * Emulation of external PID instructions # gpg: Signature made Thu 08 Nov 2018 12:14:27 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.1-20181108: (22 commits) ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HV target/ppc: Add one reg id for ptcr This patch fixes processing of rfi instructions in icount mode. hw/ppc/ppc440_uc: Remove dead code in sdram_size() MAINTAINERS: PPC: Remove myself ppc/pnv: check size before data buffer access target/ppc: fix mtmsr instruction for icount hw/ppc/mac_newworld: Free openpic_irqs array after use macio/pmu: Fix missing vmsd terminator spapr_pci: convert g_malloc() to g_new() target/ppc: Split out float_invalid_cvt target/ppc: Split out float_invalid_op_div target/ppc: Split out float_invalid_op_mul target/ppc: Split out float_invalid_op_addsub target/ppc: Introduce fp number classification target/ppc: Remove float_check_status target/ppc: Split up float_invalid_op_excp hw/ppc/spapr_rng: Introduce CONFIG_SPAPR_RNG switch for spapr_rng.c PPC: e500: convert SysBus init method to a realize method ppc4xx_pci: convert SysBus init method to a realize method ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7360be896a
30
MAINTAINERS
30
MAINTAINERS
@ -230,7 +230,6 @@ F: tests/tcg/openrisc/
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PowerPC
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M: David Gibson <david@gibson.dropbear.id.au>
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M: Alexander Graf <agraf@suse.de>
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L: qemu-ppc@nongnu.org
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S: Maintained
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F: target/ppc/
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@ -341,7 +340,7 @@ S: Maintained
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F: target/mips/kvm.c
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PPC
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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S: Maintained
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F: target/ppc/kvm.c
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@ -779,21 +778,21 @@ F: hw/openrisc/openrisc_sim.c
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PowerPC Machines
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----------------
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405
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Odd Fixes
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F: hw/ppc/ppc405_boards.c
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Bamboo
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Odd Fixes
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F: hw/ppc/ppc440_bamboo.c
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e500
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Supported
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S: Odd Fixes
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F: hw/ppc/e500.[hc]
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F: hw/ppc/e500plat.c
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F: include/hw/ppc/ppc_e500.h
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@ -801,16 +800,16 @@ F: include/hw/pci-host/ppce500.h
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F: pc-bios/u-boot.e500
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mpc8544ds
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Supported
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S: Odd Fixes
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F: hw/ppc/mpc8544ds.c
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F: hw/ppc/mpc8544_guts.c
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New World
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Maintained
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S: Odd Fixes
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F: hw/ppc/mac_newworld.c
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F: hw/pci-host/uninorth.c
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F: hw/pci-bridge/dec.[hc]
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@ -822,9 +821,9 @@ F: include/hw/misc/mos6522.h
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F: include/hw/ppc/mac_dbdma.h
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Old World
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Maintained
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S: Odd Fixes
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F: hw/ppc/mac_oldworld.c
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F: hw/pci-host/grackle.c
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F: hw/misc/macio/
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@ -849,7 +848,6 @@ F: pc-bios/ppc_rom.bin
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sPAPR
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M: David Gibson <david@gibson.dropbear.id.au>
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M: Alexander Graf <agraf@suse.de>
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L: qemu-ppc@nongnu.org
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S: Supported
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F: hw/*/spapr*
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@ -1124,7 +1122,7 @@ F: tests/acpi-test-data/*
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F: tests/acpi-test-data/*/*
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ppc4xx
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Odd Fixes
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F: hw/ppc/ppc4*.c
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@ -1133,9 +1131,9 @@ F: include/hw/ppc/ppc4xx.h
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F: include/hw/i2c/ppc4xx_i2c.h
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ppce500
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M: Alexander Graf <agraf@suse.de>
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M: David Gibson <david@gibson.dropbear.id.au>
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L: qemu-ppc@nongnu.org
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S: Supported
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S: Odd Fixes
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F: hw/ppc/e500*
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F: hw/pci-host/ppce500.c
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F: hw/net/fsl_etsec/
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@ -18,3 +18,4 @@ CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
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CONFIG_XICS_KVM=$(call land,$(CONFIG_PSERIES),$(CONFIG_KVM))
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CONFIG_MEM_DEVICE=y
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CONFIG_DIMM=y
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CONFIG_SPAPR_RNG=y
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@ -686,6 +686,7 @@ static const VMStateDescription vmstate_pmu_adb = {
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VMSTATE_TIMER_PTR(adb_poll_timer, PMUState),
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VMSTATE_UINT8(adb_reply_size, PMUState),
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VMSTATE_BUFFER(adb_reply, PMUState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -436,8 +436,9 @@ static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
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return &s->bm_as;
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}
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static int e500_pcihost_initfn(SysBusDevice *dev)
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static void e500_pcihost_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PCIHostState *h;
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PPCE500PCIState *s;
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PCIBus *b;
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@ -447,7 +448,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
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s = PPC_E500_PCI_HOST_BRIDGE(dev);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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sysbus_init_irq(sbd, &s->irq[i]);
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}
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for (i = 0; i < PCI_NUM_PINS; i++) {
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@ -460,7 +461,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
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/* PIO lives at the bottom of our bus space */
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memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
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b = pci_register_root_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
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b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
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PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
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h->bus = b;
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@ -483,10 +484,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
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memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
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memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
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memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
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sysbus_init_mmio(dev, &s->container);
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sysbus_init_mmio(sbd, &s->container);
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pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
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return 0;
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}
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static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
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@ -526,9 +525,8 @@ static Property pcihost_properties[] = {
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static void e500_pcihost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = e500_pcihost_initfn;
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dc->realize = e500_pcihost_realize;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->props = pcihost_properties;
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dc->vmsd = &vmstate_ppce500_pci;
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@ -3,8 +3,9 @@ obj-y += ppc.o ppc_booke.o fdt.o
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# IBM pSeries (sPAPR)
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obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o
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obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
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obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
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obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o
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obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o
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obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o
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# IBM PowerNV
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obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
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ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
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@ -303,6 +303,7 @@ static void ppc_core99_init(MachineState *machine)
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sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
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}
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}
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g_free(openpic_irqs);
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if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
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/* 970 gets a U3 bus */
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@ -155,9 +155,15 @@ static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
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/* XXX Check for magic bits at the top, addr size etc... */
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unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
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uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
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uint8_t data[4];
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uint8_t data[8];
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bool success;
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if (sz > sizeof(data)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
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return;
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}
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if (cmd & ECCB_CTL_READ) {
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success = opb_read(lpc, opb_addr, data, sz);
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if (success) {
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@ -466,17 +466,18 @@ const MemoryRegionOps ppc440_pcix_host_data_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int ppc440_pcix_initfn(SysBusDevice *dev)
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static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PPC440PCIXState *s;
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PCIHostState *h;
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h = PCI_HOST_BRIDGE(dev);
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s = PPC440_PCIX_HOST_BRIDGE(dev);
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
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h->bus = pci_register_root_bus(DEVICE(dev), NULL, ppc440_pcix_set_irq,
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h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq,
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ppc440_pcix_map_irq, &s->irq, &s->busmem,
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get_system_io(), PCI_DEVFN(0, 0), 1, TYPE_PCI_BUS);
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@ -497,17 +498,14 @@ static int ppc440_pcix_initfn(SysBusDevice *dev)
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memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
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memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
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memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
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sysbus_init_mmio(dev, &s->container);
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return 0;
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sysbus_init_mmio(sbd, &s->container);
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}
|
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static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
|
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{
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
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DeviceClass *dc = DEVICE_CLASS(klass);
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|
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k->init = ppc440_pcix_initfn;
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dc->realize = ppc440_pcix_realize;
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dc->reset = ppc440_pcix_reset;
|
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}
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@ -559,11 +559,7 @@ static target_ulong sdram_size(uint32_t bcr)
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int sh;
|
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|
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sh = 1024 - ((bcr >> 6) & 0x3ff);
|
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if (sh == 0) {
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size = -1;
|
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} else {
|
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size = 8 * MiB * sh;
|
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}
|
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size = 8 * MiB * sh;
|
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|
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return size;
|
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}
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@ -300,8 +300,9 @@ static const VMStateDescription vmstate_ppc4xx_pci = {
|
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};
|
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|
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/* XXX Interrupt acknowledge cycles not supported. */
|
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static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
|
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static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
|
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{
|
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
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PPC4xxPCIState *s;
|
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PCIHostState *h;
|
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PCIBus *b;
|
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@ -311,10 +312,10 @@ static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
|
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s = PPC4xx_PCI_HOST_BRIDGE(dev);
|
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
|
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sysbus_init_irq(dev, &s->irq[i]);
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sysbus_init_irq(sbd, &s->irq[i]);
|
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}
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|
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b = pci_register_root_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
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b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
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ppc4xx_pci_map_irq, s->irq, get_system_memory(),
|
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get_system_io(), 0, 4, TYPE_PCI_BUS);
|
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h->bus = b;
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@ -332,10 +333,8 @@ static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
|
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memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
|
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memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
|
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memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
|
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sysbus_init_mmio(dev, &s->container);
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sysbus_init_mmio(sbd, &s->container);
|
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qemu_register_reset(ppc4xx_pci_reset, s);
|
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|
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return 0;
|
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}
|
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|
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static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
|
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@ -367,10 +366,9 @@ static const TypeInfo ppc4xx_host_bridge_info = {
|
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|
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static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
|
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{
|
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
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DeviceClass *dc = DEVICE_CLASS(klass);
|
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|
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k->init = ppc4xx_pcihost_initfn;
|
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dc->realize = ppc4xx_pcihost_realize;
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dc->vmsd = &vmstate_ppc4xx_pci;
|
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}
|
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|
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|
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@ -610,6 +610,29 @@ static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
|
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g_free(rev);
|
||||
}
|
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|
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static int spapr_rng_populate_dt(void *fdt)
|
||||
{
|
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int node;
|
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int ret;
|
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|
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node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
|
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if (node <= 0) {
|
||||
return -1;
|
||||
}
|
||||
ret = fdt_setprop_string(fdt, node, "device_type",
|
||||
"ibm,platform-facilities");
|
||||
ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
|
||||
ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
|
||||
|
||||
node = fdt_add_subnode(fdt, node, "ibm,random-v1");
|
||||
if (node <= 0) {
|
||||
return -1;
|
||||
}
|
||||
ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
|
||||
|
||||
return ret ? -1 : 0;
|
||||
}
|
||||
|
||||
static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
|
||||
{
|
||||
MemoryDeviceInfoList *info;
|
||||
@ -1915,6 +1938,7 @@ static const VMStateDescription vmstate_spapr = {
|
||||
&vmstate_spapr_cap_sbbc,
|
||||
&vmstate_spapr_cap_ibs,
|
||||
&vmstate_spapr_irq_map,
|
||||
&vmstate_spapr_cap_nested_kvm_hv,
|
||||
NULL
|
||||
}
|
||||
};
|
||||
@ -3879,6 +3903,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
|
||||
smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
|
||||
smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
|
||||
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
|
||||
smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
|
||||
spapr_caps_add_properties(smc, &error_abort);
|
||||
smc->irq = &spapr_irq_xics;
|
||||
}
|
||||
|
||||
@ -368,6 +368,28 @@ static void cap_hpt_maxpagesize_cpu_apply(sPAPRMachineState *spapr,
|
||||
ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift);
|
||||
}
|
||||
|
||||
static void cap_nested_kvm_hv_apply(sPAPRMachineState *spapr,
|
||||
uint8_t val, Error **errp)
|
||||
{
|
||||
if (!val) {
|
||||
/* capability disabled by default */
|
||||
return;
|
||||
}
|
||||
|
||||
if (tcg_enabled()) {
|
||||
error_setg(errp,
|
||||
"No Nested KVM-HV support in tcg, try cap-nested-hv=off");
|
||||
} else if (kvm_enabled()) {
|
||||
if (!kvmppc_has_cap_nested_kvm_hv()) {
|
||||
error_setg(errp,
|
||||
"KVM implementation does not support Nested KVM-HV, try cap-nested-hv=off");
|
||||
} else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
|
||||
error_setg(errp,
|
||||
"Error enabling cap-nested-hv with KVM, try cap-nested-hv=off");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
|
||||
[SPAPR_CAP_HTM] = {
|
||||
.name = "htm",
|
||||
@ -437,6 +459,15 @@ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
|
||||
.apply = cap_hpt_maxpagesize_apply,
|
||||
.cpu_apply = cap_hpt_maxpagesize_cpu_apply,
|
||||
},
|
||||
[SPAPR_CAP_NESTED_KVM_HV] = {
|
||||
.name = "nested-hv",
|
||||
.description = "Allow Nested KVM-HV",
|
||||
.index = SPAPR_CAP_NESTED_KVM_HV,
|
||||
.get = spapr_cap_get_bool,
|
||||
.set = spapr_cap_set_bool,
|
||||
.type = "bool",
|
||||
.apply = cap_nested_kvm_hv_apply,
|
||||
},
|
||||
};
|
||||
|
||||
static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
|
||||
@ -564,6 +595,7 @@ SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP);
|
||||
SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC);
|
||||
SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
|
||||
SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
|
||||
SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
|
||||
|
||||
void spapr_caps_init(sPAPRMachineState *spapr)
|
||||
{
|
||||
|
||||
@ -1882,7 +1882,7 @@ static int spapr_pci_pre_save(void *opaque)
|
||||
if (!sphb->msi_devs_num) {
|
||||
return 0;
|
||||
}
|
||||
sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig));
|
||||
sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num);
|
||||
|
||||
g_hash_table_iter_init(&iter, sphb->msi);
|
||||
for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
|
||||
|
||||
@ -132,29 +132,6 @@ static void spapr_rng_realize(DeviceState *dev, Error **errp)
|
||||
}
|
||||
}
|
||||
|
||||
int spapr_rng_populate_dt(void *fdt)
|
||||
{
|
||||
int node;
|
||||
int ret;
|
||||
|
||||
node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
|
||||
if (node <= 0) {
|
||||
return -1;
|
||||
}
|
||||
ret = fdt_setprop_string(fdt, node, "device_type",
|
||||
"ibm,platform-facilities");
|
||||
ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
|
||||
ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
|
||||
|
||||
node = fdt_add_subnode(fdt, node, "ibm,random-v1");
|
||||
if (node <= 0) {
|
||||
return -1;
|
||||
}
|
||||
ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
|
||||
|
||||
return ret ? -1 : 0;
|
||||
}
|
||||
|
||||
static Property spapr_rng_properties[] = {
|
||||
DEFINE_PROP_BOOL("use-kvm", sPAPRRngState, use_kvm, false),
|
||||
DEFINE_PROP_LINK("rng", sPAPRRngState, backend, TYPE_RNG_BACKEND,
|
||||
|
||||
@ -70,8 +70,10 @@ typedef enum {
|
||||
#define SPAPR_CAP_IBS 0x05
|
||||
/* HPT Maximum Page Size (encoded as a shift) */
|
||||
#define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
|
||||
/* Nested KVM-HV */
|
||||
#define SPAPR_CAP_NESTED_KVM_HV 0x07
|
||||
/* Num Caps */
|
||||
#define SPAPR_CAP_NUM (SPAPR_CAP_HPT_MAXPAGESIZE + 1)
|
||||
#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_KVM_HV + 1)
|
||||
|
||||
/*
|
||||
* Capability Values
|
||||
@ -745,8 +747,6 @@ int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
|
||||
|
||||
#define TYPE_SPAPR_RNG "spapr-rng"
|
||||
|
||||
int spapr_rng_populate_dt(void *fdt);
|
||||
|
||||
#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
|
||||
|
||||
/*
|
||||
@ -793,6 +793,7 @@ extern const VMStateDescription vmstate_spapr_cap_dfp;
|
||||
extern const VMStateDescription vmstate_spapr_cap_cfpc;
|
||||
extern const VMStateDescription vmstate_spapr_cap_sbbc;
|
||||
extern const VMStateDescription vmstate_spapr_cap_ibs;
|
||||
extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
|
||||
|
||||
static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
|
||||
{
|
||||
|
||||
@ -918,6 +918,19 @@ enum {
|
||||
/* number of possible TLBs */
|
||||
#define BOOKE206_MAX_TLBN 4
|
||||
|
||||
#define EPID_EPID_SHIFT 0x0
|
||||
#define EPID_EPID 0xFF
|
||||
#define EPID_ELPID_SHIFT 0x10
|
||||
#define EPID_ELPID 0x3F0000
|
||||
#define EPID_EGS 0x20000000
|
||||
#define EPID_EGS_SHIFT 29
|
||||
#define EPID_EAS 0x40000000
|
||||
#define EPID_EAS_SHIFT 30
|
||||
#define EPID_EPR 0x80000000
|
||||
#define EPID_EPR_SHIFT 31
|
||||
/* We don't support EGS and ELPID */
|
||||
#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Server and Embedded Processor Control */
|
||||
|
||||
@ -947,7 +960,16 @@ struct ppc_radix_page_info {
|
||||
|
||||
/*****************************************************************************/
|
||||
/* The whole PowerPC CPU context */
|
||||
#define NB_MMU_MODES 8
|
||||
|
||||
/* PowerPC needs eight modes for different hypervisor/supervisor/guest +
|
||||
* real/paged mode combinations. The other two modes are for external PID
|
||||
* load/store.
|
||||
*/
|
||||
#define NB_MMU_MODES 10
|
||||
#define MMU_MODE8_SUFFIX _epl
|
||||
#define MMU_MODE9_SUFFIX _eps
|
||||
#define PPC_TLB_EPID_LOAD 8
|
||||
#define PPC_TLB_EPID_STORE 9
|
||||
|
||||
#define PPC_CPU_OPCODES_LEN 0x40
|
||||
#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -29,7 +29,9 @@ DEF_HELPER_4(lsw, void, env, tl, i32, i32)
|
||||
DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, i32)
|
||||
DEF_HELPER_FLAGS_3(dcbzep, TCG_CALL_NO_WG, void, env, tl, i32)
|
||||
DEF_HELPER_FLAGS_2(icbi, TCG_CALL_NO_WG, void, env, tl)
|
||||
DEF_HELPER_FLAGS_2(icbiep, TCG_CALL_NO_WG, void, env, tl)
|
||||
DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
@ -658,6 +660,8 @@ DEF_HELPER_2(booke206_tlbilx1, void, env, tl)
|
||||
DEF_HELPER_2(booke206_tlbilx3, void, env, tl)
|
||||
DEF_HELPER_2(booke206_tlbflush, void, env, tl)
|
||||
DEF_HELPER_3(booke_setpid, void, env, i32, tl)
|
||||
DEF_HELPER_2(booke_set_eplc, void, env, tl)
|
||||
DEF_HELPER_2(booke_set_epsc, void, env, tl)
|
||||
DEF_HELPER_2(6xx_tlbd, void, env, tl)
|
||||
DEF_HELPER_2(6xx_tlbi, void, env, tl)
|
||||
DEF_HELPER_2(74xx_tlbd, void, env, tl)
|
||||
|
||||
@ -91,6 +91,7 @@ static int cap_ppc_pvr_compat;
|
||||
static int cap_ppc_safe_cache;
|
||||
static int cap_ppc_safe_bounds_check;
|
||||
static int cap_ppc_safe_indirect_branch;
|
||||
static int cap_ppc_nested_kvm_hv;
|
||||
|
||||
static uint32_t debug_inst_opcode;
|
||||
|
||||
@ -150,6 +151,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
|
||||
cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
|
||||
cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
|
||||
kvmppc_get_cpu_characteristics(s);
|
||||
cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
|
||||
/*
|
||||
* Note: setting it to false because there is not such capability
|
||||
* in KVM at this moment.
|
||||
@ -2422,6 +2424,16 @@ int kvmppc_get_cap_safe_indirect_branch(void)
|
||||
return cap_ppc_safe_indirect_branch;
|
||||
}
|
||||
|
||||
bool kvmppc_has_cap_nested_kvm_hv(void)
|
||||
{
|
||||
return !!cap_ppc_nested_kvm_hv;
|
||||
}
|
||||
|
||||
int kvmppc_set_cap_nested_kvm_hv(int enable)
|
||||
{
|
||||
return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
|
||||
}
|
||||
|
||||
bool kvmppc_has_cap_spapr_vfio(void)
|
||||
{
|
||||
return cap_spapr_vfio;
|
||||
|
||||
@ -62,6 +62,8 @@ bool kvmppc_has_cap_mmu_hash_v3(void);
|
||||
int kvmppc_get_cap_safe_cache(void);
|
||||
int kvmppc_get_cap_safe_bounds_check(void);
|
||||
int kvmppc_get_cap_safe_indirect_branch(void);
|
||||
bool kvmppc_has_cap_nested_kvm_hv(void);
|
||||
int kvmppc_set_cap_nested_kvm_hv(int enable);
|
||||
int kvmppc_enable_hwrng(void);
|
||||
int kvmppc_put_books_sregs(PowerPCCPU *cpu);
|
||||
PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void);
|
||||
@ -320,6 +322,16 @@ static inline int kvmppc_get_cap_safe_indirect_branch(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool kvmppc_has_cap_nested_kvm_hv(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int kvmppc_set_cap_nested_kvm_hv(int enable)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int kvmppc_enable_hwrng(void)
|
||||
{
|
||||
return -1;
|
||||
|
||||
@ -142,11 +142,13 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
|
||||
}
|
||||
}
|
||||
|
||||
void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
|
||||
static void dcbz_common(CPUPPCState *env, target_ulong addr,
|
||||
uint32_t opcode, bool epid, uintptr_t retaddr)
|
||||
{
|
||||
target_ulong mask, dcbz_size = env->dcache_line_size;
|
||||
uint32_t i;
|
||||
void *haddr;
|
||||
int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx;
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
/* Check for dcbz vs dcbzl on 970 */
|
||||
@ -166,17 +168,34 @@ void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
|
||||
}
|
||||
|
||||
/* Try fast path translate */
|
||||
haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx);
|
||||
haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx);
|
||||
if (haddr) {
|
||||
memset(haddr, 0, dcbz_size);
|
||||
} else {
|
||||
/* Slow path */
|
||||
for (i = 0; i < dcbz_size; i += 8) {
|
||||
cpu_stq_data_ra(env, addr + i, 0, GETPC());
|
||||
if (epid) {
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* Does not make sense on USER_ONLY config */
|
||||
cpu_stq_eps_ra(env, addr + i, 0, retaddr);
|
||||
#endif
|
||||
} else {
|
||||
cpu_stq_data_ra(env, addr + i, 0, retaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
|
||||
{
|
||||
dcbz_common(env, addr, opcode, false, GETPC());
|
||||
}
|
||||
|
||||
void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
|
||||
{
|
||||
dcbz_common(env, addr, opcode, true, GETPC());
|
||||
}
|
||||
|
||||
void helper_icbi(CPUPPCState *env, target_ulong addr)
|
||||
{
|
||||
addr &= ~(env->dcache_line_size - 1);
|
||||
@ -188,6 +207,15 @@ void helper_icbi(CPUPPCState *env, target_ulong addr)
|
||||
cpu_ldl_data_ra(env, addr, GETPC());
|
||||
}
|
||||
|
||||
void helper_icbiep(CPUPPCState *env, target_ulong addr)
|
||||
{
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* See comments above */
|
||||
addr &= ~(env->dcache_line_size - 1);
|
||||
cpu_ldl_epl_ra(env, addr, GETPC());
|
||||
#endif
|
||||
}
|
||||
|
||||
/* XXX: to be tested */
|
||||
target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
|
||||
uint32_t ra, uint32_t rb)
|
||||
|
||||
@ -924,29 +924,84 @@ static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool is_epid_mmu(int mmu_idx)
|
||||
{
|
||||
return mmu_idx == PPC_TLB_EPID_STORE || mmu_idx == PPC_TLB_EPID_LOAD;
|
||||
}
|
||||
|
||||
static uint32_t mmubooke206_esr(int mmu_idx, bool rw)
|
||||
{
|
||||
uint32_t esr = 0;
|
||||
if (rw) {
|
||||
esr |= ESR_ST;
|
||||
}
|
||||
if (is_epid_mmu(mmu_idx)) {
|
||||
esr |= ESR_EPID;
|
||||
}
|
||||
return esr;
|
||||
}
|
||||
|
||||
/* Get EPID register given the mmu_idx. If this is regular load,
|
||||
* construct the EPID access bits from current processor state */
|
||||
|
||||
/* Get the effective AS and PR bits and the PID. The PID is returned only if
|
||||
* EPID load is requested, otherwise the caller must detect the correct EPID.
|
||||
* Return true if valid EPID is returned. */
|
||||
static bool mmubooke206_get_as(CPUPPCState *env,
|
||||
int mmu_idx, uint32_t *epid_out,
|
||||
bool *as_out, bool *pr_out)
|
||||
{
|
||||
if (is_epid_mmu(mmu_idx)) {
|
||||
uint32_t epidr;
|
||||
if (mmu_idx == PPC_TLB_EPID_STORE) {
|
||||
epidr = env->spr[SPR_BOOKE_EPSC];
|
||||
} else {
|
||||
epidr = env->spr[SPR_BOOKE_EPLC];
|
||||
}
|
||||
*epid_out = (epidr & EPID_EPID) >> EPID_EPID_SHIFT;
|
||||
*as_out = !!(epidr & EPID_EAS);
|
||||
*pr_out = !!(epidr & EPID_EPR);
|
||||
return true;
|
||||
} else {
|
||||
*as_out = msr_ds;
|
||||
*pr_out = msr_pr;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if the tlb found by hashing really matches */
|
||||
static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
|
||||
hwaddr *raddr, int *prot,
|
||||
target_ulong address, int rw,
|
||||
int access_type)
|
||||
int access_type, int mmu_idx)
|
||||
{
|
||||
int ret;
|
||||
int prot2 = 0;
|
||||
uint32_t epid;
|
||||
bool as, pr;
|
||||
bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
|
||||
|
||||
if (ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID]) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
if (!use_epid) {
|
||||
if (ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID]) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
|
||||
if (env->spr[SPR_BOOKE_PID1] &&
|
||||
ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID1]) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
if (env->spr[SPR_BOOKE_PID1] &&
|
||||
ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID1]) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
|
||||
if (env->spr[SPR_BOOKE_PID2] &&
|
||||
ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID2]) >= 0) {
|
||||
goto found_tlb;
|
||||
if (env->spr[SPR_BOOKE_PID2] &&
|
||||
ppcmas_tlb_check(env, tlb, raddr, address,
|
||||
env->spr[SPR_BOOKE_PID2]) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
} else {
|
||||
if (ppcmas_tlb_check(env, tlb, raddr, address, epid) >= 0) {
|
||||
goto found_tlb;
|
||||
}
|
||||
}
|
||||
|
||||
LOG_SWTLB("%s: TLB entry not found\n", __func__);
|
||||
@ -954,7 +1009,7 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
|
||||
|
||||
found_tlb:
|
||||
|
||||
if (msr_pr != 0) {
|
||||
if (pr) {
|
||||
if (tlb->mas7_3 & MAS3_UR) {
|
||||
prot2 |= PAGE_READ;
|
||||
}
|
||||
@ -978,6 +1033,8 @@ found_tlb:
|
||||
|
||||
/* Check the address space and permissions */
|
||||
if (access_type == ACCESS_CODE) {
|
||||
/* There is no way to fetch code using epid load */
|
||||
assert(!use_epid);
|
||||
if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
|
||||
LOG_SWTLB("%s: AS doesn't match\n", __func__);
|
||||
return -1;
|
||||
@ -992,7 +1049,7 @@ found_tlb:
|
||||
LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
|
||||
ret = -3;
|
||||
} else {
|
||||
if (msr_dr != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
|
||||
if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
|
||||
LOG_SWTLB("%s: AS doesn't match\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
@ -1012,7 +1069,7 @@ found_tlb:
|
||||
|
||||
static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
target_ulong address, int rw,
|
||||
int access_type)
|
||||
int access_type, int mmu_idx)
|
||||
{
|
||||
ppcmas_tlb_t *tlb;
|
||||
hwaddr raddr;
|
||||
@ -1030,7 +1087,7 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
continue;
|
||||
}
|
||||
ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
|
||||
rw, access_type);
|
||||
rw, access_type, mmu_idx);
|
||||
if (ret != -1) {
|
||||
goto found_tlb;
|
||||
}
|
||||
@ -1348,8 +1405,10 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
target_ulong eaddr, int rw, int access_type)
|
||||
static int get_physical_address_wtlb(
|
||||
CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
target_ulong eaddr, int rw, int access_type,
|
||||
int mmu_idx)
|
||||
{
|
||||
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||
int ret = -1;
|
||||
@ -1392,7 +1451,7 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
break;
|
||||
case POWERPC_MMU_BOOKE206:
|
||||
ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
|
||||
access_type);
|
||||
access_type, mmu_idx);
|
||||
break;
|
||||
case POWERPC_MMU_MPC8xx:
|
||||
/* XXX: TODO */
|
||||
@ -1417,6 +1476,13 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_physical_address(
|
||||
CPUPPCState *env, mmu_ctx_t *ctx,
|
||||
target_ulong eaddr, int rw, int access_type)
|
||||
{
|
||||
return get_physical_address_wtlb(env, ctx, eaddr, rw, access_type, 0);
|
||||
}
|
||||
|
||||
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
||||
{
|
||||
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
||||
@ -1463,8 +1529,15 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
||||
}
|
||||
|
||||
static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
|
||||
int rw)
|
||||
int rw, int mmu_idx)
|
||||
{
|
||||
uint32_t epid;
|
||||
bool as, pr;
|
||||
uint32_t missed_tid = 0;
|
||||
bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
|
||||
if (rw == 2) {
|
||||
as = msr_ir;
|
||||
}
|
||||
env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
|
||||
env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
|
||||
env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
|
||||
@ -1473,7 +1546,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
|
||||
env->spr[SPR_BOOKE_MAS7] = 0;
|
||||
|
||||
/* AS */
|
||||
if (((rw == 2) && msr_ir) || ((rw != 2) && msr_dr)) {
|
||||
if (as) {
|
||||
env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
|
||||
env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
|
||||
}
|
||||
@ -1481,19 +1554,25 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
|
||||
env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
|
||||
env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
|
||||
|
||||
switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
|
||||
case MAS4_TIDSELD_PID0:
|
||||
env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID] << MAS1_TID_SHIFT;
|
||||
break;
|
||||
case MAS4_TIDSELD_PID1:
|
||||
env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID1] << MAS1_TID_SHIFT;
|
||||
break;
|
||||
case MAS4_TIDSELD_PID2:
|
||||
env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID2] << MAS1_TID_SHIFT;
|
||||
break;
|
||||
if (!use_epid) {
|
||||
switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
|
||||
case MAS4_TIDSELD_PID0:
|
||||
missed_tid = env->spr[SPR_BOOKE_PID];
|
||||
break;
|
||||
case MAS4_TIDSELD_PID1:
|
||||
missed_tid = env->spr[SPR_BOOKE_PID1];
|
||||
break;
|
||||
case MAS4_TIDSELD_PID2:
|
||||
missed_tid = env->spr[SPR_BOOKE_PID2];
|
||||
break;
|
||||
}
|
||||
env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
|
||||
} else {
|
||||
missed_tid = epid;
|
||||
env->spr[SPR_BOOKE_MAS6] |= missed_tid << 16;
|
||||
}
|
||||
env->spr[SPR_BOOKE_MAS1] |= (missed_tid << MAS1_TID_SHIFT);
|
||||
|
||||
env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
|
||||
|
||||
/* next victim logic */
|
||||
env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
|
||||
@ -1520,7 +1599,8 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
|
||||
/* data access */
|
||||
access_type = env->access_type;
|
||||
}
|
||||
ret = get_physical_address(env, &ctx, address, rw, access_type);
|
||||
ret = get_physical_address_wtlb(env, &ctx, address, rw,
|
||||
access_type, mmu_idx);
|
||||
if (ret == 0) {
|
||||
tlb_set_page(cs, address & TARGET_PAGE_MASK,
|
||||
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
||||
@ -1550,12 +1630,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
|
||||
env->spr[SPR_40x_ESR] = 0x00000000;
|
||||
break;
|
||||
case POWERPC_MMU_BOOKE206:
|
||||
booke206_update_mas_tlb_miss(env, address, 2);
|
||||
booke206_update_mas_tlb_miss(env, address, 2, mmu_idx);
|
||||
/* fall through */
|
||||
case POWERPC_MMU_BOOKE:
|
||||
cs->exception_index = POWERPC_EXCP_ITLB;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_BOOKE_DEAR] = address;
|
||||
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, 0);
|
||||
return -1;
|
||||
case POWERPC_MMU_MPC8xx:
|
||||
/* XXX: TODO */
|
||||
@ -1642,13 +1723,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
|
||||
cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
|
||||
break;
|
||||
case POWERPC_MMU_BOOKE206:
|
||||
booke206_update_mas_tlb_miss(env, address, rw);
|
||||
booke206_update_mas_tlb_miss(env, address, rw, mmu_idx);
|
||||
/* fall through */
|
||||
case POWERPC_MMU_BOOKE:
|
||||
cs->exception_index = POWERPC_EXCP_DTLB;
|
||||
env->error_code = 0;
|
||||
env->spr[SPR_BOOKE_DEAR] = address;
|
||||
env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
|
||||
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw);
|
||||
return -1;
|
||||
case POWERPC_MMU_REAL:
|
||||
cpu_abort(cs, "PowerPC in real mode should never raise "
|
||||
@ -1672,7 +1753,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
|
||||
} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
|
||||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
|
||||
env->spr[SPR_BOOKE_DEAR] = address;
|
||||
env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
|
||||
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, rw);
|
||||
} else {
|
||||
env->spr[SPR_DAR] = address;
|
||||
if (rw == 1) {
|
||||
@ -2598,6 +2679,19 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
|
||||
tlb_flush(CPU(cpu));
|
||||
}
|
||||
|
||||
void helper_booke_set_eplc(CPUPPCState *env, target_ulong val)
|
||||
{
|
||||
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||
env->spr[SPR_BOOKE_EPLC] = val & EPID_MASK;
|
||||
tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD);
|
||||
}
|
||||
void helper_booke_set_epsc(CPUPPCState *env, target_ulong val)
|
||||
{
|
||||
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||
env->spr[SPR_BOOKE_EPSC] = val & EPID_MASK;
|
||||
tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE);
|
||||
}
|
||||
|
||||
static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
|
||||
{
|
||||
PowerPCCPU *cpu = ppc_env_get_cpu(env);
|
||||
|
||||
@ -2579,6 +2579,26 @@ GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
|
||||
GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
|
||||
/* lwz lwzu lwzux lwzx */
|
||||
GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
|
||||
|
||||
#define GEN_LDEPX(name, ldop, opc2, opc3) \
|
||||
static void glue(gen_, name##epx)(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv EA; \
|
||||
CHK_SV; \
|
||||
gen_set_access_type(ctx, ACCESS_INT); \
|
||||
EA = tcg_temp_new(); \
|
||||
gen_addr_reg_index(ctx, EA); \
|
||||
tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
|
||||
tcg_temp_free(EA); \
|
||||
}
|
||||
|
||||
GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
|
||||
GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
|
||||
GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
/* lwaux */
|
||||
GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
|
||||
@ -2760,6 +2780,27 @@ GEN_STS(stb, st8, 0x06, PPC_INTEGER);
|
||||
GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
|
||||
/* stw stwu stwux stwx */
|
||||
GEN_STS(stw, st32, 0x04, PPC_INTEGER);
|
||||
|
||||
#define GEN_STEPX(name, stop, opc2, opc3) \
|
||||
static void glue(gen_, name##epx)(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv EA; \
|
||||
CHK_SV; \
|
||||
gen_set_access_type(ctx, ACCESS_INT); \
|
||||
EA = tcg_temp_new(); \
|
||||
gen_addr_reg_index(ctx, EA); \
|
||||
tcg_gen_qemu_st_tl( \
|
||||
cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
|
||||
tcg_temp_free(EA); \
|
||||
}
|
||||
|
||||
GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
|
||||
GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
|
||||
GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
|
||||
#endif
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
|
||||
GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
|
||||
@ -3878,9 +3919,15 @@ static void gen_rfi(DisasContext *ctx)
|
||||
}
|
||||
/* Restore CPU state */
|
||||
CHK_SV;
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_update_cfar(ctx, ctx->base.pc_next - 4);
|
||||
gen_helper_rfi(cpu_env);
|
||||
gen_sync_exception(ctx);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -3892,9 +3939,15 @@ static void gen_rfid(DisasContext *ctx)
|
||||
#else
|
||||
/* Restore CPU state */
|
||||
CHK_SV;
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_update_cfar(ctx, ctx->base.pc_next - 4);
|
||||
gen_helper_rfid(cpu_env);
|
||||
gen_sync_exception(ctx);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -4257,11 +4310,17 @@ static void gen_mtmsrd(DisasContext *ctx)
|
||||
* if we enter power saving mode, we will exit the loop
|
||||
* directly from ppc_store_msr
|
||||
*/
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_update_nip(ctx, ctx->base.pc_next);
|
||||
gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
|
||||
/* Must stop the translation as machine state (may have) changed */
|
||||
/* Note that mtmsr is not always defined as context-synchronizing */
|
||||
gen_stop_exception(ctx);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
}
|
||||
}
|
||||
#endif /* !defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
@ -4286,6 +4345,9 @@ static void gen_mtmsr(DisasContext *ctx)
|
||||
* if we enter power saving mode, we will exit the loop
|
||||
* directly from ppc_store_msr
|
||||
*/
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_update_nip(ctx, ctx->base.pc_next);
|
||||
#if defined(TARGET_PPC64)
|
||||
tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
|
||||
@ -4293,6 +4355,9 @@ static void gen_mtmsr(DisasContext *ctx)
|
||||
tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
|
||||
#endif
|
||||
gen_helper_store_msr(cpu_env, msr);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_end();
|
||||
}
|
||||
tcg_temp_free(msr);
|
||||
/* Must stop the translation as machine state (may have) changed */
|
||||
/* Note that mtmsr is not always defined as context-synchronizing */
|
||||
@ -4392,6 +4457,19 @@ static void gen_dcbf(DisasContext *ctx)
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* dcbfep (external PID dcbf) */
|
||||
static void gen_dcbfep(DisasContext *ctx)
|
||||
{
|
||||
/* XXX: specification says this is treated as a load by the MMU */
|
||||
TCGv t0;
|
||||
CHK_SV;
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
t0 = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, t0);
|
||||
tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* dcbi (Supervisor only) */
|
||||
static void gen_dcbi(DisasContext *ctx)
|
||||
{
|
||||
@ -4425,6 +4503,18 @@ static void gen_dcbst(DisasContext *ctx)
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* dcbstep (dcbstep External PID version) */
|
||||
static void gen_dcbstep(DisasContext *ctx)
|
||||
{
|
||||
/* XXX: specification say this is treated as a load by the MMU */
|
||||
TCGv t0;
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
t0 = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, t0);
|
||||
tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* dcbt */
|
||||
static void gen_dcbt(DisasContext *ctx)
|
||||
{
|
||||
@ -4434,6 +4524,15 @@ static void gen_dcbt(DisasContext *ctx)
|
||||
*/
|
||||
}
|
||||
|
||||
/* dcbtep */
|
||||
static void gen_dcbtep(DisasContext *ctx)
|
||||
{
|
||||
/* interpreted as no-op */
|
||||
/* XXX: specification say this is treated as a load by the MMU
|
||||
* but does not generate any exception
|
||||
*/
|
||||
}
|
||||
|
||||
/* dcbtst */
|
||||
static void gen_dcbtst(DisasContext *ctx)
|
||||
{
|
||||
@ -4443,6 +4542,15 @@ static void gen_dcbtst(DisasContext *ctx)
|
||||
*/
|
||||
}
|
||||
|
||||
/* dcbtstep */
|
||||
static void gen_dcbtstep(DisasContext *ctx)
|
||||
{
|
||||
/* interpreted as no-op */
|
||||
/* XXX: specification say this is treated as a load by the MMU
|
||||
* but does not generate any exception
|
||||
*/
|
||||
}
|
||||
|
||||
/* dcbtls */
|
||||
static void gen_dcbtls(DisasContext *ctx)
|
||||
{
|
||||
@ -4469,6 +4577,21 @@ static void gen_dcbz(DisasContext *ctx)
|
||||
tcg_temp_free_i32(tcgv_op);
|
||||
}
|
||||
|
||||
/* dcbzep */
|
||||
static void gen_dcbzep(DisasContext *ctx)
|
||||
{
|
||||
TCGv tcgv_addr;
|
||||
TCGv_i32 tcgv_op;
|
||||
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
tcgv_addr = tcg_temp_new();
|
||||
tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
|
||||
gen_addr_reg_index(ctx, tcgv_addr);
|
||||
gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
|
||||
tcg_temp_free(tcgv_addr);
|
||||
tcg_temp_free_i32(tcgv_op);
|
||||
}
|
||||
|
||||
/* dst / dstt */
|
||||
static void gen_dst(DisasContext *ctx)
|
||||
{
|
||||
@ -4507,6 +4630,17 @@ static void gen_icbi(DisasContext *ctx)
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* icbiep */
|
||||
static void gen_icbiep(DisasContext *ctx)
|
||||
{
|
||||
TCGv t0;
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
t0 = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, t0);
|
||||
gen_helper_icbiep(cpu_env, t0);
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
/* Optional: */
|
||||
/* dcba */
|
||||
static void gen_dcba(DisasContext *ctx)
|
||||
@ -6774,16 +6908,22 @@ GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
|
||||
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
|
||||
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
|
||||
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
|
||||
GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
|
||||
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
|
||||
GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
|
||||
GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
|
||||
GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
|
||||
GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
|
||||
GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
|
||||
GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
|
||||
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
|
||||
GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
|
||||
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
|
||||
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
|
||||
@ -7086,6 +7226,19 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
|
||||
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
|
||||
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
|
||||
|
||||
/* External PID based load */
|
||||
#undef GEN_LDEPX
|
||||
#define GEN_LDEPX(name, ldop, opc2, opc3) \
|
||||
GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
|
||||
0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
|
||||
GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
|
||||
GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
|
||||
GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
|
||||
#endif
|
||||
|
||||
#undef GEN_ST
|
||||
#undef GEN_STU
|
||||
#undef GEN_STUX
|
||||
@ -7120,6 +7273,18 @@ GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
|
||||
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
|
||||
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
|
||||
|
||||
#undef GEN_STEPX
|
||||
#define GEN_STEPX(name, ldop, opc2, opc3) \
|
||||
GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
|
||||
0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
|
||||
GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
|
||||
GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
|
||||
GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
|
||||
#endif
|
||||
|
||||
#undef GEN_CRLOGIC
|
||||
#define GEN_CRLOGIC(name, tcg_op, opc) \
|
||||
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
|
||||
|
||||
@ -673,6 +673,23 @@ GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
|
||||
/* lfs lfsu lfsux lfsx */
|
||||
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
||||
|
||||
/* lfdepx (external PID lfdx) */
|
||||
static void gen_lfdepx(DisasContext *ctx)
|
||||
{
|
||||
TCGv EA;
|
||||
CHK_SV;
|
||||
if (unlikely(!ctx->fpu_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU);
|
||||
return;
|
||||
}
|
||||
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||
EA = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, EA);
|
||||
tcg_gen_qemu_ld_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD,
|
||||
DEF_MEMOP(MO_Q));
|
||||
tcg_temp_free(EA);
|
||||
}
|
||||
|
||||
/* lfdp */
|
||||
static void gen_lfdp(DisasContext *ctx)
|
||||
{
|
||||
@ -846,6 +863,23 @@ GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
|
||||
/* stfs stfsu stfsux stfsx */
|
||||
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
|
||||
|
||||
/* stfdepx (external PID lfdx) */
|
||||
static void gen_stfdepx(DisasContext *ctx)
|
||||
{
|
||||
TCGv EA;
|
||||
CHK_SV;
|
||||
if (unlikely(!ctx->fpu_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_FPU);
|
||||
return;
|
||||
}
|
||||
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||
EA = tcg_temp_new();
|
||||
gen_addr_reg_index(ctx, EA);
|
||||
tcg_gen_qemu_st_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE,
|
||||
DEF_MEMOP(MO_Q));
|
||||
tcg_temp_free(EA);
|
||||
}
|
||||
|
||||
/* stfdp */
|
||||
static void gen_stfdp(DisasContext *ctx)
|
||||
{
|
||||
|
||||
@ -66,6 +66,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
|
||||
|
||||
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
||||
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
||||
GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
|
||||
GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
|
||||
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
|
||||
@ -87,6 +88,7 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
|
||||
GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
|
||||
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
|
||||
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
|
||||
GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
|
||||
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
|
||||
|
||||
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
|
||||
|
||||
@ -1653,6 +1653,15 @@ static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
|
||||
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void gen_spr_usprg3(CPUPPCState *env)
|
||||
@ -1912,6 +1921,16 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
|
||||
&spr_read_generic, &spr_write_booke_pid,
|
||||
0x00000000);
|
||||
}
|
||||
|
||||
spr_register(env, SPR_BOOKE_EPLC, "EPLC",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_eplc,
|
||||
0x00000000);
|
||||
spr_register(env, SPR_BOOKE_EPSC, "EPSC",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_epsc,
|
||||
0x00000000);
|
||||
|
||||
/* XXX : not implemented */
|
||||
spr_register(env, SPR_MMUCFG, "MMUCFG",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
@ -2797,8 +2816,6 @@ static void gen_spr_8xx(CPUPPCState *env)
|
||||
* perf => 768-783 (Power 2.04)
|
||||
* perf => 784-799 (Power 2.04)
|
||||
* PPR => SPR 896 (Power 2.04)
|
||||
* EPLC => SPR 947 (Power 2.04 emb)
|
||||
* EPSC => SPR 948 (Power 2.04 emb)
|
||||
* DABRX => 1015 (Power 2.04 hypv)
|
||||
* FPECR => SPR 1022 (?)
|
||||
* ... and more (thermal management, performance counters, ...)
|
||||
@ -8197,11 +8214,11 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
|
||||
{
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* Partition Table Control */
|
||||
spr_register_hv(env, SPR_PTCR, "PTCR",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_ptcr,
|
||||
0x00000000);
|
||||
spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
SPR_NOACCESS, SPR_NOACCESS,
|
||||
&spr_read_generic, &spr_write_ptcr,
|
||||
KVM_REG_PPC_PTCR, 0x00000000);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user