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target/xtensa: convert to do_transaction_failed

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2018-08-19 19:27:21 -07:00
parent 9a124b6927
commit 76b7dd641f
4 changed files with 35 additions and 16 deletions
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2
target/xtensa/cpu.c
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@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#else #else
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_unassigned_access = xtensa_cpu_do_unassigned_access; cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif #endif
cc->debug_excp_handler = xtensa_breakpoint_handler; cc->debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info; cc->disas_set_info = xtensa_cpu_disas_set_info;

7
target/xtensa/cpu.h
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@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
int mmu_idx); int mmu_idx);
void xtensa_cpu_do_interrupt(CPUState *cpu); void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
bool is_write, bool is_exec, int opaque, unsigned size, MMUAccessType access_type,
unsigned size); int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags); fprintf_function cpu_fprintf, int flags);
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

30
target/xtensa/helper.c
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@ -566,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_write)
} }
} }
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx, uint32_t vaddr, int is_write, int mmu_idx,
@ -584,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { may_lookup_pt && get_pte(env, vaddr, &pte)) {
ring = (pte >> 4) & 0x3; ring = (pte >> 4) & 0x3;
wi = 0; wi = 0;
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
@ -631,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
return 0; return 0;
} }
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{ {
CPUState *cs = CPU(xtensa_env_get_cpu(env)); CPUState *cs = CPU(xtensa_env_get_cpu(env));
uint32_t paddr; uint32_t paddr;
@ -642,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
&paddr, &page_size, &access, false); &paddr, &page_size, &access, false);
qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", if (ret == 0) {
__func__, vaddr, ret ? ~0 : paddr); qemu_log_mask(CPU_LOG_MMU,
"%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
__func__, vaddr, pt_vaddr, paddr);
} else {
qemu_log_mask(CPU_LOG_MMU,
"%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
__func__, vaddr, pt_vaddr, ret);
}
if (ret == 0) { if (ret == 0) {
*pte = ldl_phys(cs->as, paddr); MemTxResult result;
*pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
&result);
if (result != MEMTX_OK) {
qemu_log_mask(CPU_LOG_MMU,
"%s: couldn't load PTE: transaction failed (%u)\n",
__func__, (unsigned)result);
ret = 1;
}
} }
return ret; return ret == 0;
} }
static int get_physical_addr_region(CPUXtensaState *env, static int get_physical_addr_region(CPUXtensaState *env,

12
target/xtensa/op_helper.c
View File

@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
} }
} }
void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr, void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
bool is_write, bool is_exec, int opaque, unsigned size, MMUAccessType access_type,
unsigned size) int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{ {
XtensaCPU *cpu = XTENSA_CPU(cs); XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env; CPUXtensaState *env = &cpu->env;
cpu_restore_state(cs, retaddr, true);
HELPER(exception_cause_vaddr)(env, env->pc, HELPER(exception_cause_vaddr)(env, env->pc,
is_exec ? access_type == MMU_INST_FETCH ?
INSTR_PIF_ADDR_ERROR_CAUSE : INSTR_PIF_ADDR_ERROR_CAUSE :
LOAD_STORE_PIF_ADDR_ERROR_CAUSE, LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
is_exec ? addr : cs->mem_io_vaddr); addr);
} }
static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)