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target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows

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When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2022-08-22 14:23:49 +01:00 committed by Richard Henderson
parent bb7d902154
commit 76e25d41d4
1 changed files with 1 additions and 1 deletions
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2
target/arm/helper.c
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@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env)
uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1ull << 63 : 1ull << 31;
if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
env->cp15.c9_pmovsr |= (1 << 31);
env->cp15.c9_pmovsr |= (1ULL << 31);
pmu_update_irq(env);
}