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lm32: uart model
This patch add support for the LatticeMico32 UART. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Michael Walle
Edgar E. Iglesias
parent
ea7924dcc4
commit
770ae5713a
@ -251,6 +251,7 @@ obj-ppc-y += xilinx_ethlite.o
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obj-lm32-y += lm32_pic.o
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obj-lm32-y += lm32_juart.o
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obj-lm32-y += lm32_timer.o
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obj-lm32-y += lm32_uart.o
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obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
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obj-mips-y += mips_addr.o mips_timer.o mips_int.o
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288
hw/lm32_uart.c
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288
hw/lm32_uart.c
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@ -0,0 +1,288 @@
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/*
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* QEMU model of the LatticeMico32 UART block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.latticesemi.com/documents/mico32uart.pdf
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-char.h"
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#include "qemu-error.h"
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enum {
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R_RXTX = 0,
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R_IER,
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R_IIR,
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R_LCR,
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R_MCR,
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R_LSR,
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R_MSR,
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R_DIV,
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R_MAX
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};
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enum {
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IER_RBRI = (1<<0),
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IER_THRI = (1<<1),
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IER_RLSI = (1<<2),
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IER_MSI = (1<<3),
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};
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enum {
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IIR_STAT = (1<<0),
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IIR_ID0 = (1<<1),
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IIR_ID1 = (1<<2),
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};
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enum {
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LCR_WLS0 = (1<<0),
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LCR_WLS1 = (1<<1),
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LCR_STB = (1<<2),
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LCR_PEN = (1<<3),
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LCR_EPS = (1<<4),
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LCR_SP = (1<<5),
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LCR_SB = (1<<6),
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};
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enum {
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MCR_DTR = (1<<0),
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MCR_RTS = (1<<1),
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};
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enum {
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LSR_DR = (1<<0),
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LSR_OE = (1<<1),
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LSR_PE = (1<<2),
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LSR_FE = (1<<3),
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LSR_BI = (1<<4),
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LSR_THRE = (1<<5),
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LSR_TEMT = (1<<6),
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};
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enum {
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MSR_DCTS = (1<<0),
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MSR_DDSR = (1<<1),
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MSR_TERI = (1<<2),
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MSR_DDCD = (1<<3),
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MSR_CTS = (1<<4),
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MSR_DSR = (1<<5),
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MSR_RI = (1<<6),
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MSR_DCD = (1<<7),
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};
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struct LM32UartState {
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SysBusDevice busdev;
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t regs[R_MAX];
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};
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typedef struct LM32UartState LM32UartState;
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static void uart_update_irq(LM32UartState *s)
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{
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unsigned int irq;
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if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
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&& (s->regs[R_IER] & IER_RLSI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
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} else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID1;
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} else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID0;
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} else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
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irq = 1;
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s->regs[R_IIR] = 0;
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} else {
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irq = 0;
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s->regs[R_IIR] = IIR_STAT;
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}
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trace_lm32_uart_irq_state(irq);
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qemu_set_irq(s->irq, irq);
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}
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static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
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{
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LM32UartState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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r = s->regs[R_RXTX];
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s->regs[R_LSR] &= ~LSR_DR;
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uart_update_irq(s);
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break;
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case R_IIR:
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case R_LSR:
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case R_MSR:
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r = s->regs[addr];
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break;
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case R_IER:
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case R_LCR:
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case R_MCR:
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case R_DIV:
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error_report("lm32_uart: read access to write only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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error_report("lm32_uart: read access to unkown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_lm32_uart_memory_read(addr << 2, r);
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return r;
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}
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static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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LM32UartState *s = opaque;
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unsigned char ch = value;
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trace_lm32_uart_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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qemu_chr_write(s->chr, &ch, 1);
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}
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break;
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case R_IER:
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case R_LCR:
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case R_MCR:
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case R_DIV:
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s->regs[addr] = value;
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break;
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case R_IIR:
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case R_LSR:
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case R_MSR:
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error_report("lm32_uart: write access to read only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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error_report("lm32_uart: write access to unkown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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uart_update_irq(s);
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}
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static CPUReadMemoryFunc * const uart_read_fn[] = {
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NULL,
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NULL,
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&uart_read,
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};
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static CPUWriteMemoryFunc * const uart_write_fn[] = {
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NULL,
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NULL,
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&uart_write,
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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LM32UartState *s = opaque;
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if (s->regs[R_LSR] & LSR_DR) {
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s->regs[R_LSR] |= LSR_OE;
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}
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s->regs[R_LSR] |= LSR_DR;
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s->regs[R_RXTX] = *buf;
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uart_update_irq(s);
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}
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static int uart_can_rx(void *opaque)
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{
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LM32UartState *s = opaque;
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return !(s->regs[R_LSR] & LSR_DR);
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static void uart_reset(DeviceState *d)
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{
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LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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/* defaults */
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s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
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}
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static int lm32_uart_init(SysBusDevice *dev)
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{
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LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
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int uart_regs;
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sysbus_init_irq(dev, &s->irq);
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uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
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s->chr = qdev_init_chardev(&dev->qdev);
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_lm32_uart = {
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.name = "lm32-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static SysBusDeviceInfo lm32_uart_info = {
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.init = lm32_uart_init,
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.qdev.name = "lm32-uart",
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.qdev.size = sizeof(LM32UartState),
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.qdev.vmsd = &vmstate_lm32_uart,
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.qdev.reset = uart_reset,
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};
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static void lm32_uart_register(void)
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{
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sysbus_register_withprop(&lm32_uart_info);
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}
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device_init(lm32_uart_register)
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@ -275,3 +275,8 @@ disable lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x valu
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disable lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_timer_hit(void) "timer hit"
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disable lm32_timer_irq_state(int level) "irq state %d"
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# hw/lm32_uart.c
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disable lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_irq_state(int level) "irq state %d"
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