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megasas: Fixup MSI-X handling
MSI-X works slightly different than INTx; the doorbell registers are not necessarily used as MSI-X interrupts are directed anyway. So the head pointer on the reply queue needs to be updated as soon as a frame is completed, and we can set the doorbell only when in INTx mode. Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -545,34 +545,41 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
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* Context is opaque, but emulation is running in
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* little endian. So convert it.
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*/
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tail = s->reply_queue_head;
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if (megasas_use_queue64(s)) {
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queue_offset = tail * sizeof(uint64_t);
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queue_offset = s->reply_queue_head * sizeof(uint64_t);
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stq_le_phys(&address_space_memory,
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s->reply_queue_pa + queue_offset, context);
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} else {
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queue_offset = tail * sizeof(uint32_t);
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queue_offset = s->reply_queue_head * sizeof(uint32_t);
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stl_le_phys(&address_space_memory,
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s->reply_queue_pa + queue_offset, context);
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}
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s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
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s->reply_queue_tail = ldl_le_phys(&address_space_memory,
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s->consumer_pa);
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trace_megasas_qf_complete(context, s->reply_queue_head,
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s->reply_queue_tail, s->busy, s->doorbell);
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s->reply_queue_tail, s->busy);
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}
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if (megasas_intr_enabled(s)) {
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/* Update reply queue pointer */
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s->reply_queue_tail = ldl_le_phys(&address_space_memory,
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s->consumer_pa);
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tail = s->reply_queue_head;
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s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
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trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
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s->busy);
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stl_le_phys(&address_space_memory,
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s->producer_pa, s->reply_queue_head);
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/* Notify HBA */
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s->doorbell++;
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if (s->doorbell == 1) {
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if (msix_enabled(pci_dev)) {
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trace_megasas_msix_raise(0);
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msix_notify(pci_dev, 0);
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} else if (msi_enabled(pci_dev)) {
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trace_megasas_msi_raise(0);
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msi_notify(pci_dev, 0);
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} else {
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if (msix_enabled(pci_dev)) {
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trace_megasas_msix_raise(0);
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msix_notify(pci_dev, 0);
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} else if (msi_enabled(pci_dev)) {
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trace_megasas_msi_raise(0);
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msi_notify(pci_dev, 0);
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} else {
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s->doorbell++;
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if (s->doorbell == 1) {
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trace_megasas_irq_raise();
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pci_irq_assert(pci_dev);
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}
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@ -2028,7 +2035,7 @@ static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
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trace_megasas_mmio_readl("MFI_OMSK", retval);
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break;
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case MFI_ODCR0:
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retval = s->doorbell;
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retval = s->doorbell ? 1 : 0;
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trace_megasas_mmio_readl("MFI_ODCR0", retval);
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break;
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case MFI_DIAG:
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@ -2103,15 +2110,8 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
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case MFI_ODCR0:
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trace_megasas_mmio_writel("MFI_ODCR0", val);
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s->doorbell = 0;
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if (s->producer_pa && megasas_intr_enabled(s)) {
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/* Update reply queue pointer */
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s->reply_queue_tail = ldl_le_phys(&address_space_memory,
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s->consumer_pa);
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trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
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s->busy);
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stl_le_phys(&address_space_memory,
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s->producer_pa, s->reply_queue_head);
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if (!msix_enabled(pci_dev)) {
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if (megasas_intr_enabled(s)) {
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if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
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trace_megasas_irq_lower();
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pci_irq_deassert(pci_dev);
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}
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@ -706,7 +706,7 @@ megasas_qf_enqueue(unsigned int index, unsigned int count, uint64_t context, uns
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megasas_qf_update(unsigned int head, unsigned int tail, unsigned int busy) "head %x tail %x busy %d"
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megasas_qf_map_failed(int cmd, unsigned long frame) "scmd %d: frame %lu"
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megasas_qf_complete_noirq(uint64_t context) "context %" PRIx64 " "
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megasas_qf_complete(uint64_t context, unsigned int head, unsigned int tail, int busy, unsigned int doorbell) "context %" PRIx64 " head %x tail %x busy %d doorbell %x"
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megasas_qf_complete(uint64_t context, unsigned int head, unsigned int tail, int busy) "context %" PRIx64 " head %x tail %x busy %d"
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megasas_frame_busy(uint64_t addr) "frame %" PRIx64 " busy"
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megasas_unhandled_frame_cmd(int cmd, uint8_t frame_cmd) "scmd %d: MFI cmd %x"
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megasas_handle_scsi(const char *frame, int bus, int dev, int lun, void *sdev, unsigned long size) "%s dev %x/%x/%x sdev %p xfer %lu"
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