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tcg/s390x: Implement tcg_out_dup*_vec
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
b33ce7251c
commit
79cada8693
@ -265,13 +265,20 @@ typedef enum S390Opcode {
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RX_STC = 0x42,
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RX_STH = 0x40,
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VRIa_VGBM = 0xe744,
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VRIa_VREPI = 0xe745,
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VRIb_VGM = 0xe746,
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VRIc_VREP = 0xe74d,
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VRRa_VLR = 0xe756,
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VRRf_VLVGP = 0xe762,
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VRSb_VLVG = 0xe722,
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VRSc_VLGV = 0xe721,
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VRX_VL = 0xe706,
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VRX_VLLEZ = 0xe704,
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VRX_VLREP = 0xe705,
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VRX_VST = 0xe70e,
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VRX_VSTEF = 0xe70b,
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VRX_VSTEG = 0xe70a,
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@ -563,6 +570,34 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
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| ((v4 & 0x10) << (4 + 0));
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}
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static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op,
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TCGReg v1, uint16_t i2, int m3)
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{
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tcg_debug_assert(is_vector_reg(v1));
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tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
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tcg_out16(s, i2);
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tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
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}
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static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op,
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TCGReg v1, uint8_t i2, uint8_t i3, int m4)
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{
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tcg_debug_assert(is_vector_reg(v1));
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tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
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tcg_out16(s, (i2 << 8) | (i3 & 0xff));
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tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
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}
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static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op,
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TCGReg v1, uint16_t i2, TCGReg v3, int m4)
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{
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tcg_debug_assert(is_vector_reg(v1));
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tcg_debug_assert(is_vector_reg(v3));
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tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
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tcg_out16(s, i2);
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tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
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}
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static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
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TCGReg v1, TCGReg v2, int m3)
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{
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@ -572,6 +607,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
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tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
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}
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static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
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TCGReg v1, TCGReg r2, TCGReg r3)
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{
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tcg_debug_assert(is_vector_reg(v1));
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tcg_debug_assert(is_general_reg(r2));
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tcg_debug_assert(is_general_reg(r3));
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tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2);
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tcg_out16(s, r3 << 12);
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tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
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}
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static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
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intptr_t d2, TCGReg b2, TCGReg r3, int m4)
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{
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@ -2501,19 +2547,89 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, TCGReg src)
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{
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g_assert_not_reached();
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if (is_general_reg(src)) {
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/* Replicate general register into two MO_64. */
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tcg_out_insn(s, VRRf, VLVGP, dst, src, src);
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if (vece == MO_64) {
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return true;
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}
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}
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/*
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* Recall that the "standard" integer, within a vector, is the
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* rightmost element of the leftmost doubleword, a-la VLLEZ.
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*/
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tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece);
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return true;
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}
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static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, TCGReg base, intptr_t offset)
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{
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g_assert_not_reached();
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tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece);
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return true;
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}
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static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
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TCGReg dst, int64_t val)
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{
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g_assert_not_reached();
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int i, mask, msb, lsb;
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/* Look for int16_t elements. */
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if (vece <= MO_16 ||
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(vece == MO_32 ? (int32_t)val : val) == (int16_t)val) {
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tcg_out_insn(s, VRIa, VREPI, dst, val, vece);
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return;
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}
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/* Look for bit masks. */
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if (vece == MO_32) {
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if (risbg_mask((int32_t)val)) {
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/* Handle wraparound by swapping msb and lsb. */
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if ((val & 0x80000001u) == 0x80000001u) {
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msb = 32 - ctz32(~val);
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lsb = clz32(~val) - 1;
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} else {
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msb = clz32(val);
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lsb = 31 - ctz32(val);
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}
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tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
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return;
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}
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} else {
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if (risbg_mask(val)) {
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/* Handle wraparound by swapping msb and lsb. */
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if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
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/* Handle wraparound by swapping msb and lsb. */
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msb = 64 - ctz64(~val);
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lsb = clz64(~val) - 1;
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} else {
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msb = clz64(val);
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lsb = 63 - ctz64(val);
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}
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tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
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return;
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}
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}
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/* Look for all bytes 0x00 or 0xff. */
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for (i = mask = 0; i < 8; i++) {
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uint8_t byte = val >> (i * 8);
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if (byte == 0xff) {
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mask |= 1 << i;
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} else if (byte != 0) {
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break;
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}
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}
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if (i == 8) {
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tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0);
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return;
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}
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/* Otherwise, stuff it in the constant pool. */
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tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0);
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new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2);
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tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64);
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}
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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