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s390: Add channel I/O instructions.
Provide handlers for (most) channel I/O instructions. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Cornelia Huck
Alexander Graf
parent
5d69c547d9
commit
7b18aad543
@ -147,6 +147,9 @@ static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
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}
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#endif
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/* distinguish between 24 bit and 31 bit addressing */
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#define HIGH_ORDER_BIT 0x80000000
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/* Interrupt Codes */
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/* Program Interrupts */
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#define PGM_OPERATION 0x0001
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@ -331,6 +334,20 @@ void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
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int is_write);
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void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
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int is_write);
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static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
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{
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hwaddr addr = 0;
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uint8_t reg;
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reg = ipb >> 28;
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if (reg > 0) {
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addr = env->regs[reg];
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}
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addr += (ipb >> 16) & 0xfff;
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return addr;
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}
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void s390x_tod_timer(void *opaque);
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void s390x_cpu_timer(void *opaque);
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@ -380,6 +397,89 @@ static inline unsigned s390_del_running_cpu(CPUS390XState *env)
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void cpu_lock(void);
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void cpu_unlock(void);
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typedef struct SubchDev SubchDev;
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static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
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uint16_t schid)
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{
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return NULL;
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}
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static inline bool css_subch_visible(SubchDev *sch)
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{
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return false;
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}
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static inline void css_conditional_io_interrupt(SubchDev *sch)
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{
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}
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static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
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{
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return -ENODEV;
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}
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static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
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{
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return true;
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}
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static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
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{
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return -ENODEV;
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}
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static inline int css_do_xsch(SubchDev *sch)
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{
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return -ENODEV;
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}
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static inline int css_do_csch(SubchDev *sch)
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{
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return -ENODEV;
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}
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static inline int css_do_hsch(SubchDev *sch)
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{
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return -ENODEV;
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}
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static inline int css_do_ssch(SubchDev *sch, ORB *orb)
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{
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return -ENODEV;
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}
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static inline int css_do_tsch(SubchDev *sch, IRB *irb)
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{
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return -ENODEV;
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}
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static inline int css_do_stcrw(CRW *crw)
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{
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return 1;
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}
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static inline int css_do_tpi(uint64_t addr, int lowcore)
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{
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return 0;
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}
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static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
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int rfmt, uint8_t l_chpid, void *buf)
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{
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return 0;
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}
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static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
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{
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}
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static inline int css_enable_mss(void)
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{
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return -EINVAL;
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}
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static inline int css_enable_mcsse(void)
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{
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return -EINVAL;
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}
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static inline int css_do_rsch(SubchDev *sch)
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{
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return -ENODEV;
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}
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static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
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{
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return -ENODEV;
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}
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static inline bool css_present(uint8_t cssid)
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{
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return false;
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}
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static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
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{
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env->aregs[0] = newtls >> 32;
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@ -13,6 +13,7 @@
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#include "cpu.h"
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#include "ioinst.h"
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#include "trace.h"
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int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
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int *schid)
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@ -34,3 +35,718 @@ int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
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*schid = IOINST_SCHID_NR(value);
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return 0;
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}
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int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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int ret = -ENODEV;
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int cc;
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("xsch", cssid, ssid, schid);
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_xsch(sch);
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}
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switch (ret) {
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case -ENODEV:
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cc = 3;
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break;
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case -EBUSY:
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cc = 2;
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break;
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case 0:
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cc = 0;
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break;
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default:
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cc = 1;
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break;
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}
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return cc;
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}
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int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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int ret = -ENODEV;
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int cc;
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("csch", cssid, ssid, schid);
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_csch(sch);
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}
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if (ret == -ENODEV) {
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cc = 3;
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} else {
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cc = 0;
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}
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return cc;
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}
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int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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int ret = -ENODEV;
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int cc;
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("hsch", cssid, ssid, schid);
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_hsch(sch);
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}
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switch (ret) {
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case -ENODEV:
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cc = 3;
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break;
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case -EBUSY:
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cc = 2;
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break;
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case 0:
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cc = 0;
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break;
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default:
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cc = 1;
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break;
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}
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return cc;
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}
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static int ioinst_schib_valid(SCHIB *schib)
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{
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if ((schib->pmcw.flags & PMCW_FLAGS_MASK_INVALID) ||
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(schib->pmcw.chars & PMCW_CHARS_MASK_INVALID)) {
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return 0;
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}
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/* Disallow extended measurements for now. */
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if (schib->pmcw.chars & PMCW_CHARS_MASK_XMWME) {
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return 0;
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}
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return 1;
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}
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int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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SCHIB *schib;
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uint64_t addr;
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int ret = -ENODEV;
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int cc;
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hwaddr len = sizeof(*schib);
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("msch", cssid, ssid, schid);
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addr = decode_basedisp_s(env, ipb);
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schib = s390_cpu_physical_memory_map(env, addr, &len, 0);
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if (!schib || len != sizeof(*schib)) {
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program_interrupt(env, PGM_SPECIFICATION, 2);
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cc = -EIO;
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goto out;
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}
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if (!ioinst_schib_valid(schib)) {
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program_interrupt(env, PGM_OPERAND, 2);
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cc = -EIO;
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goto out;
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}
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_msch(sch, schib);
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}
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switch (ret) {
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case -ENODEV:
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cc = 3;
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break;
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case -EBUSY:
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cc = 2;
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break;
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case 0:
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cc = 0;
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break;
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default:
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cc = 1;
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break;
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}
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out:
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s390_cpu_physical_memory_unmap(env, schib, len, 0);
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return cc;
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}
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static void copy_orb_from_guest(ORB *dest, const ORB *src)
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{
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dest->intparm = be32_to_cpu(src->intparm);
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dest->ctrl0 = be16_to_cpu(src->ctrl0);
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dest->lpm = src->lpm;
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dest->ctrl1 = src->ctrl1;
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dest->cpa = be32_to_cpu(src->cpa);
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}
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static int ioinst_orb_valid(ORB *orb)
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{
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if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
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(orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
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return 0;
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}
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if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
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return 0;
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}
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return 1;
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}
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int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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ORB *orig_orb, orb;
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uint64_t addr;
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int ret = -ENODEV;
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int cc;
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hwaddr len = sizeof(*orig_orb);
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("ssch", cssid, ssid, schid);
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addr = decode_basedisp_s(env, ipb);
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orig_orb = s390_cpu_physical_memory_map(env, addr, &len, 0);
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if (!orig_orb || len != sizeof(*orig_orb)) {
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program_interrupt(env, PGM_SPECIFICATION, 2);
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cc = -EIO;
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goto out;
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}
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copy_orb_from_guest(&orb, orig_orb);
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if (!ioinst_orb_valid(&orb)) {
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program_interrupt(env, PGM_OPERAND, 2);
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cc = -EIO;
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goto out;
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}
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_ssch(sch, &orb);
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}
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switch (ret) {
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case -ENODEV:
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cc = 3;
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break;
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case -EBUSY:
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cc = 2;
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break;
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case 0:
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cc = 0;
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break;
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default:
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cc = 1;
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break;
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}
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out:
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s390_cpu_physical_memory_unmap(env, orig_orb, len, 0);
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return cc;
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}
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int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb)
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{
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CRW *crw;
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uint64_t addr;
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int cc;
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hwaddr len = sizeof(*crw);
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addr = decode_basedisp_s(env, ipb);
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crw = s390_cpu_physical_memory_map(env, addr, &len, 1);
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if (!crw || len != sizeof(*crw)) {
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program_interrupt(env, PGM_SPECIFICATION, 2);
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cc = -EIO;
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goto out;
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}
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cc = css_do_stcrw(crw);
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/* 0 - crw stored, 1 - zeroes stored */
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out:
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s390_cpu_physical_memory_unmap(env, crw, len, 1);
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return cc;
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}
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int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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uint64_t addr;
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int cc;
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SCHIB *schib;
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hwaddr len = sizeof(*schib);
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("stsch", cssid, ssid, schid);
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addr = decode_basedisp_s(env, ipb);
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schib = s390_cpu_physical_memory_map(env, addr, &len, 1);
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if (!schib || len != sizeof(*schib)) {
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program_interrupt(env, PGM_SPECIFICATION, 2);
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cc = -EIO;
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goto out;
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}
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch) {
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if (css_subch_visible(sch)) {
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css_do_stsch(sch, schib);
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cc = 0;
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} else {
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/* Indicate no more subchannels in this css/ss */
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cc = 3;
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}
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} else {
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if (css_schid_final(cssid, ssid, schid)) {
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cc = 3; /* No more subchannels in this css/ss */
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} else {
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/* Store an empty schib. */
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memset(schib, 0, sizeof(*schib));
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cc = 0;
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}
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}
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out:
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s390_cpu_physical_memory_unmap(env, schib, len, 1);
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return cc;
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}
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int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
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{
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int cssid, ssid, schid, m;
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SubchDev *sch;
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IRB *irb;
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uint64_t addr;
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int ret = -ENODEV;
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int cc;
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hwaddr len = sizeof(*irb);
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if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
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program_interrupt(env, PGM_OPERAND, 2);
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return -EIO;
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}
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trace_ioinst_sch_id("tsch", cssid, ssid, schid);
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addr = decode_basedisp_s(env, ipb);
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irb = s390_cpu_physical_memory_map(env, addr, &len, 1);
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if (!irb || len != sizeof(*irb)) {
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program_interrupt(env, PGM_SPECIFICATION, 2);
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cc = -EIO;
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goto out;
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}
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sch = css_find_subch(m, cssid, ssid, schid);
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if (sch && css_subch_visible(sch)) {
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ret = css_do_tsch(sch, irb);
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/* 0 - status pending, 1 - not status pending */
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cc = ret;
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} else {
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cc = 3;
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}
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out:
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s390_cpu_physical_memory_unmap(env, irb, sizeof(*irb), 1);
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return cc;
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}
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typedef struct ChscReq {
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uint16_t len;
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uint16_t command;
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uint32_t param0;
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uint32_t param1;
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uint32_t param2;
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} QEMU_PACKED ChscReq;
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typedef struct ChscResp {
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uint16_t len;
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uint16_t code;
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uint32_t param;
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char data[0];
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} QEMU_PACKED ChscResp;
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#define CHSC_MIN_RESP_LEN 0x0008
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#define CHSC_SCPD 0x0002
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#define CHSC_SCSC 0x0010
|
||||
#define CHSC_SDA 0x0031
|
||||
|
||||
#define CHSC_SCPD_0_M 0x20000000
|
||||
#define CHSC_SCPD_0_C 0x10000000
|
||||
#define CHSC_SCPD_0_FMT 0x0f000000
|
||||
#define CHSC_SCPD_0_CSSID 0x00ff0000
|
||||
#define CHSC_SCPD_0_RFMT 0x00000f00
|
||||
#define CHSC_SCPD_0_RES 0xc000f000
|
||||
#define CHSC_SCPD_1_RES 0xffffff00
|
||||
#define CHSC_SCPD_01_CHPID 0x000000ff
|
||||
static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
|
||||
{
|
||||
uint16_t len = be16_to_cpu(req->len);
|
||||
uint32_t param0 = be32_to_cpu(req->param0);
|
||||
uint32_t param1 = be32_to_cpu(req->param1);
|
||||
uint16_t resp_code;
|
||||
int rfmt;
|
||||
uint16_t cssid;
|
||||
uint8_t f_chpid, l_chpid;
|
||||
int desc_size;
|
||||
int m;
|
||||
|
||||
rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
|
||||
if ((rfmt == 0) || (rfmt == 1)) {
|
||||
rfmt = !!(param0 & CHSC_SCPD_0_C);
|
||||
}
|
||||
if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
|
||||
(param1 & CHSC_SCPD_1_RES) || req->param2) {
|
||||
resp_code = 0x0003;
|
||||
goto out_err;
|
||||
}
|
||||
if (param0 & CHSC_SCPD_0_FMT) {
|
||||
resp_code = 0x0007;
|
||||
goto out_err;
|
||||
}
|
||||
cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
|
||||
m = param0 & CHSC_SCPD_0_M;
|
||||
if (cssid != 0) {
|
||||
if (!m || !css_present(cssid)) {
|
||||
resp_code = 0x0008;
|
||||
goto out_err;
|
||||
}
|
||||
}
|
||||
f_chpid = param0 & CHSC_SCPD_01_CHPID;
|
||||
l_chpid = param1 & CHSC_SCPD_01_CHPID;
|
||||
if (l_chpid < f_chpid) {
|
||||
resp_code = 0x0003;
|
||||
goto out_err;
|
||||
}
|
||||
/* css_collect_chp_desc() is endian-aware */
|
||||
desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
|
||||
&res->data);
|
||||
res->code = cpu_to_be16(0x0001);
|
||||
res->len = cpu_to_be16(8 + desc_size);
|
||||
res->param = cpu_to_be32(rfmt);
|
||||
return;
|
||||
|
||||
out_err:
|
||||
res->code = cpu_to_be16(resp_code);
|
||||
res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
|
||||
res->param = cpu_to_be32(rfmt);
|
||||
}
|
||||
|
||||
#define CHSC_SCSC_0_M 0x20000000
|
||||
#define CHSC_SCSC_0_FMT 0x000f0000
|
||||
#define CHSC_SCSC_0_CSSID 0x0000ff00
|
||||
#define CHSC_SCSC_0_RES 0xdff000ff
|
||||
static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
|
||||
{
|
||||
uint16_t len = be16_to_cpu(req->len);
|
||||
uint32_t param0 = be32_to_cpu(req->param0);
|
||||
uint8_t cssid;
|
||||
uint16_t resp_code;
|
||||
uint32_t general_chars[510];
|
||||
uint32_t chsc_chars[508];
|
||||
|
||||
if (len != 0x0010) {
|
||||
resp_code = 0x0003;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
if (param0 & CHSC_SCSC_0_FMT) {
|
||||
resp_code = 0x0007;
|
||||
goto out_err;
|
||||
}
|
||||
cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
|
||||
if (cssid != 0) {
|
||||
if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
|
||||
resp_code = 0x0008;
|
||||
goto out_err;
|
||||
}
|
||||
}
|
||||
if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
|
||||
resp_code = 0x0003;
|
||||
goto out_err;
|
||||
}
|
||||
res->code = cpu_to_be16(0x0001);
|
||||
res->len = cpu_to_be16(4080);
|
||||
res->param = 0;
|
||||
|
||||
memset(general_chars, 0, sizeof(general_chars));
|
||||
memset(chsc_chars, 0, sizeof(chsc_chars));
|
||||
|
||||
general_chars[0] = cpu_to_be32(0x03000000);
|
||||
general_chars[1] = cpu_to_be32(0x00059000);
|
||||
|
||||
chsc_chars[0] = cpu_to_be32(0x40000000);
|
||||
chsc_chars[3] = cpu_to_be32(0x00040000);
|
||||
|
||||
memcpy(res->data, general_chars, sizeof(general_chars));
|
||||
memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
|
||||
return;
|
||||
|
||||
out_err:
|
||||
res->code = cpu_to_be16(resp_code);
|
||||
res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
|
||||
res->param = 0;
|
||||
}
|
||||
|
||||
#define CHSC_SDA_0_FMT 0x0f000000
|
||||
#define CHSC_SDA_0_OC 0x0000ffff
|
||||
#define CHSC_SDA_0_RES 0xf0ff0000
|
||||
#define CHSC_SDA_OC_MCSSE 0x0
|
||||
#define CHSC_SDA_OC_MSS 0x2
|
||||
static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
|
||||
{
|
||||
uint16_t resp_code = 0x0001;
|
||||
uint16_t len = be16_to_cpu(req->len);
|
||||
uint32_t param0 = be32_to_cpu(req->param0);
|
||||
uint16_t oc;
|
||||
int ret;
|
||||
|
||||
if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
|
||||
resp_code = 0x0003;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (param0 & CHSC_SDA_0_FMT) {
|
||||
resp_code = 0x0007;
|
||||
goto out;
|
||||
}
|
||||
|
||||
oc = param0 & CHSC_SDA_0_OC;
|
||||
switch (oc) {
|
||||
case CHSC_SDA_OC_MCSSE:
|
||||
ret = css_enable_mcsse();
|
||||
if (ret == -EINVAL) {
|
||||
resp_code = 0x0101;
|
||||
goto out;
|
||||
}
|
||||
break;
|
||||
case CHSC_SDA_OC_MSS:
|
||||
ret = css_enable_mss();
|
||||
if (ret == -EINVAL) {
|
||||
resp_code = 0x0101;
|
||||
goto out;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
resp_code = 0x0003;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
res->code = cpu_to_be16(resp_code);
|
||||
res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
|
||||
res->param = 0;
|
||||
}
|
||||
|
||||
static void ioinst_handle_chsc_unimplemented(ChscResp *res)
|
||||
{
|
||||
res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
|
||||
res->code = cpu_to_be16(0x0004);
|
||||
res->param = 0;
|
||||
}
|
||||
|
||||
int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb)
|
||||
{
|
||||
ChscReq *req;
|
||||
ChscResp *res;
|
||||
uint64_t addr;
|
||||
int reg;
|
||||
uint16_t len;
|
||||
uint16_t command;
|
||||
hwaddr map_size = TARGET_PAGE_SIZE;
|
||||
int ret = 0;
|
||||
|
||||
trace_ioinst("chsc");
|
||||
reg = (ipb >> 20) & 0x00f;
|
||||
addr = env->regs[reg];
|
||||
/* Page boundary? */
|
||||
if (addr & 0xfff) {
|
||||
program_interrupt(env, PGM_SPECIFICATION, 2);
|
||||
return -EIO;
|
||||
}
|
||||
req = s390_cpu_physical_memory_map(env, addr, &map_size, 1);
|
||||
if (!req || map_size != TARGET_PAGE_SIZE) {
|
||||
program_interrupt(env, PGM_SPECIFICATION, 2);
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
len = be16_to_cpu(req->len);
|
||||
/* Length field valid? */
|
||||
if ((len < 16) || (len > 4088) || (len & 7)) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
|
||||
res = (void *)((char *)req + len);
|
||||
command = be16_to_cpu(req->command);
|
||||
trace_ioinst_chsc_cmd(command, len);
|
||||
switch (command) {
|
||||
case CHSC_SCSC:
|
||||
ioinst_handle_chsc_scsc(req, res);
|
||||
break;
|
||||
case CHSC_SCPD:
|
||||
ioinst_handle_chsc_scpd(req, res);
|
||||
break;
|
||||
case CHSC_SDA:
|
||||
ioinst_handle_chsc_sda(req, res);
|
||||
break;
|
||||
default:
|
||||
ioinst_handle_chsc_unimplemented(res);
|
||||
break;
|
||||
}
|
||||
|
||||
out:
|
||||
s390_cpu_physical_memory_unmap(env, req, map_size, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb)
|
||||
{
|
||||
uint64_t addr;
|
||||
int lowcore;
|
||||
|
||||
trace_ioinst("tpi");
|
||||
addr = decode_basedisp_s(env, ipb);
|
||||
lowcore = addr ? 0 : 1;
|
||||
if (addr < 8192) {
|
||||
addr += env->psa;
|
||||
} else if ((env->psa <= addr) && (addr < env->psa + 8192)) {
|
||||
addr -= env->psa;
|
||||
}
|
||||
return css_do_tpi(addr, lowcore);
|
||||
}
|
||||
|
||||
#define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
|
||||
#define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
|
||||
#define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
|
||||
#define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
|
||||
|
||||
int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
|
||||
uint32_t ipb)
|
||||
{
|
||||
uint8_t mbk;
|
||||
int update;
|
||||
int dct;
|
||||
|
||||
trace_ioinst("schm");
|
||||
|
||||
if (SCHM_REG1_RES(reg1)) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mbk = SCHM_REG1_MBK(reg1);
|
||||
update = SCHM_REG1_UPD(reg1);
|
||||
dct = SCHM_REG1_DCT(reg1);
|
||||
|
||||
if (update && (reg2 & 0x0000000000000fff)) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
css_do_schm(mbk, update, dct, update ? reg2 : 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1)
|
||||
{
|
||||
int cssid, ssid, schid, m;
|
||||
SubchDev *sch;
|
||||
int ret = -ENODEV;
|
||||
int cc;
|
||||
|
||||
if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
trace_ioinst_sch_id("rsch", cssid, ssid, schid);
|
||||
sch = css_find_subch(m, cssid, ssid, schid);
|
||||
if (sch && css_subch_visible(sch)) {
|
||||
ret = css_do_rsch(sch);
|
||||
}
|
||||
switch (ret) {
|
||||
case -ENODEV:
|
||||
cc = 3;
|
||||
break;
|
||||
case -EINVAL:
|
||||
cc = 2;
|
||||
break;
|
||||
case 0:
|
||||
cc = 0;
|
||||
break;
|
||||
default:
|
||||
cc = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
return cc;
|
||||
|
||||
}
|
||||
|
||||
#define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
|
||||
#define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
|
||||
#define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
|
||||
int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1)
|
||||
{
|
||||
int cc;
|
||||
uint8_t cssid;
|
||||
uint8_t chpid;
|
||||
int ret;
|
||||
|
||||
if (RCHP_REG1_RES(reg1)) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
cssid = RCHP_REG1_CSSID(reg1);
|
||||
chpid = RCHP_REG1_CHPID(reg1);
|
||||
|
||||
trace_ioinst_chp_id("rchp", cssid, chpid);
|
||||
|
||||
ret = css_do_rchp(cssid, chpid);
|
||||
|
||||
switch (ret) {
|
||||
case -ENODEV:
|
||||
cc = 3;
|
||||
break;
|
||||
case -EBUSY:
|
||||
cc = 2;
|
||||
break;
|
||||
case 0:
|
||||
cc = 0;
|
||||
break;
|
||||
default:
|
||||
/* Invalid channel subsystem. */
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return cc;
|
||||
}
|
||||
|
||||
#define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
|
||||
int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1)
|
||||
{
|
||||
/* We do not provide address limit checking, so let's suppress it. */
|
||||
if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
|
||||
program_interrupt(env, PGM_OPERAND, 2);
|
||||
return -EIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -204,4 +204,20 @@ typedef struct CRW {
|
||||
|
||||
int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
|
||||
int *schid);
|
||||
int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1);
|
||||
int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1);
|
||||
int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1);
|
||||
int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
|
||||
int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
|
||||
int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb);
|
||||
int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
|
||||
int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
|
||||
int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb);
|
||||
int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb);
|
||||
int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
|
||||
uint32_t ipb);
|
||||
int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1);
|
||||
int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1);
|
||||
int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1);
|
||||
|
||||
#endif
|
||||
|
||||
@ -1072,3 +1072,9 @@ xics_ics_eoi(int nr) "ics_eoi: irq %#x"
|
||||
hbitmap_iter_skip_words(const void *hb, void *hbi, uint64_t pos, unsigned long cur) "hb %p hbi %p pos %"PRId64" cur 0x%lx"
|
||||
hbitmap_reset(void *hb, uint64_t start, uint64_t count, uint64_t sbit, uint64_t ebit) "hb %p items %"PRIu64",%"PRIu64" bits %"PRIu64"..%"PRIu64
|
||||
hbitmap_set(void *hb, uint64_t start, uint64_t count, uint64_t sbit, uint64_t ebit) "hb %p items %"PRIu64",%"PRIu64" bits %"PRIu64"..%"PRIu64
|
||||
|
||||
# target-s390x/ioinst.c
|
||||
ioinst(const char *insn) "IOINST: %s"
|
||||
ioinst_sch_id(const char *insn, int cssid, int ssid, int schid) "IOINST: %s (%x.%x.%04x)"
|
||||
ioinst_chp_id(const char *insn, int cssid, int chpid) "IOINST: %s (%x.%02x)"
|
||||
ioinst_chsc_cmd(uint16_t cmd, uint16_t len) "IOINST: chsc command %04x, len %04x"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user