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tcg: Add atomic128 helpers
Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing paths that use it. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
c482cb117c
commit
7ebee43ee3
@ -18,7 +18,11 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if DATA_SIZE == 8
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#if DATA_SIZE == 16
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# define SUFFIX o
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# define DATA_TYPE Int128
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# define BSWAP bswap128
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#elif DATA_SIZE == 8
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# define SUFFIX q
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# define DATA_TYPE uint64_t
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# define BSWAP bswap64
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@ -61,6 +65,21 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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return atomic_cmpxchg__nocheck(haddr, cmpv, newv);
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}
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#if DATA_SIZE >= 16
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ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
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{
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DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
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__atomic_load(haddr, &val, __ATOMIC_RELAXED);
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return val;
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}
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void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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__atomic_store(haddr, &val, __ATOMIC_RELAXED);
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}
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#else
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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@ -86,6 +105,8 @@ GEN_ATOMIC_HELPER(or_fetch)
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GEN_ATOMIC_HELPER(xor_fetch)
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#undef GEN_ATOMIC_HELPER
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#endif /* DATA SIZE >= 16 */
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#undef END
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#if DATA_SIZE > 1
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@ -105,6 +126,22 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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return BSWAP(atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)));
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}
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#if DATA_SIZE >= 16
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ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
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{
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DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
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__atomic_load(haddr, &val, __ATOMIC_RELAXED);
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return BSWAP(val);
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}
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void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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val = BSWAP(val);
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__atomic_store(haddr, &val, __ATOMIC_RELAXED);
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}
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#else
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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@ -166,6 +203,7 @@ ABI_TYPE ATOMIC_NAME(add_fetch)(CPUArchState *env, target_ulong addr,
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ldo = ldn;
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}
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}
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#endif /* DATA_SIZE >= 16 */
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#undef END
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#endif /* DATA_SIZE > 1 */
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29
configure
vendored
29
configure
vendored
@ -1216,7 +1216,10 @@ case "$cpu" in
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cc_i386='$(CC) -m32'
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;;
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x86_64)
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CPU_CFLAGS="-m64"
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# ??? Only extremely old AMD cpus do not have cmpxchg16b.
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# If we truly care, we should simply detect this case at
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# runtime and generate the fallback to serial emulation.
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CPU_CFLAGS="-m64 -mcx16"
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LDFLAGS="-m64 $LDFLAGS"
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cc_i386='$(CC) -m32'
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;;
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@ -4521,6 +4524,26 @@ if compile_prog "" "" ; then
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int128=yes
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fi
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#########################################
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# See if 128-bit atomic operations are supported.
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atomic128=no
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if test "$int128" = "yes"; then
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cat > $TMPC << EOF
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int main(void)
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{
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unsigned __int128 x = 0, y = 0;
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y = __atomic_load_16(&x, 0);
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__atomic_store_16(&x, y, 0);
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__atomic_compare_exchange_16(&x, &y, x, 0, 0, 0);
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return 0;
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}
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EOF
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if compile_prog "" "" ; then
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atomic128=yes
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fi
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fi
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########################################
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# check if getauxval is available.
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@ -5483,6 +5506,10 @@ if test "$int128" = "yes" ; then
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echo "CONFIG_INT128=y" >> $config_host_mak
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fi
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if test "$atomic128" = "yes" ; then
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echo "CONFIG_ATOMIC128=y" >> $config_host_mak
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fi
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if test "$getauxval" = "yes" ; then
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echo "CONFIG_GETAUXVAL=y" >> $config_host_mak
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fi
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5
cputlb.c
5
cputlb.c
@ -690,6 +690,11 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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#define DATA_SIZE 8
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#include "atomic_template.h"
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#ifdef CONFIG_ATOMIC128
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#define DATA_SIZE 16
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#include "atomic_template.h"
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#endif
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/* Second set of helpers are directly callable from TCG as helpers. */
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#undef EXTRA_ARGS
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@ -2,6 +2,7 @@
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#define INT128_H
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#ifdef CONFIG_INT128
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#include "qemu/bswap.h"
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typedef __int128_t Int128;
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@ -137,6 +138,11 @@ static inline void int128_subfrom(Int128 *a, Int128 b)
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*a -= b;
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}
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static inline Int128 bswap128(Int128 a)
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{
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return int128_make128(bswap64(int128_gethi(a)), bswap64(int128_getlo(a)));
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}
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#else /* !CONFIG_INT128 */
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typedef struct Int128 Int128;
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@ -133,4 +133,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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#define DATA_SIZE 8
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#include "atomic_template.h"
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/* The following is only callable from other helpers, and matches up
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with the softmmu version. */
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#ifdef CONFIG_ATOMIC128
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#undef EXTRA_ARGS
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#undef ATOMIC_NAME
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#undef ATOMIC_MMU_LOOKUP
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#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
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#define ATOMIC_NAME(X) \
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HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
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#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
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#define DATA_SIZE 16
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#include "atomic_template.h"
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#endif /* CONFIG_ATOMIC128 */
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#endif /* !CONFIG_SOFTMMU */
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24
tcg/tcg.h
24
tcg/tcg.h
@ -1229,7 +1229,29 @@ GEN_ATOMIC_HELPER_ALL(xchg)
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#undef GEN_ATOMIC_HELPER_ALL
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#undef GEN_ATOMIC_HELPER
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#endif /* CONFIG_SOFTMMU */
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#ifdef CONFIG_ATOMIC128
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#include "qemu/int128.h"
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/* These aren't really a "proper" helpers because TCG cannot manage Int128.
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However, use the same format as the others, for use by the backends. */
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Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
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Int128 cmpv, Int128 newv,
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TCGMemOpIdx oi, uintptr_t retaddr);
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Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
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Int128 cmpv, Int128 newv,
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TCGMemOpIdx oi, uintptr_t retaddr);
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Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr);
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Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr);
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void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
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TCGMemOpIdx oi, uintptr_t retaddr);
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void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
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TCGMemOpIdx oi, uintptr_t retaddr);
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#endif /* CONFIG_ATOMIC128 */
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#endif /* TCG_H */
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