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PPC: clean up ppc405

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Rely on the subpage system instead of the local version.
Make most functions "static".
Fix wrong parameter passed to ppc4xx_pob_reset.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-08-15 14:27:05 +00:00
parent 1786dc15ee
commit 802670e6c9
8 changed files with 79 additions and 349 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/pc.h
View File

@ -12,12 +12,6 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister);
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
/* parallel.c */

2
hw/ppc.h
View File

@ -45,3 +45,5 @@ enum {
#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
#define PPC_SERIAL_MM_BAUDBASE 399193

29
hw/ppc405.h
View File

@ -59,35 +59,6 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
/* PowerPC 4xx peripheral local bus arbitrer */
void ppc4xx_plb_init (CPUState *env);
/* PLB to OPB bridge */
void ppc4xx_pob_init (CPUState *env);
/* OPB arbitrer */
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset);
/* Peripheral controller */
void ppc405_ebc_init (CPUState *env);
/* DMA controller */
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
/* GPIO */
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset);
/* Serial ports */
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq,
CharDriverState *chr);
/* On Chip Memory */
void ppc405_ocm_init (CPUState *env);
/* I2C controller */
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq);
/* General purpose timers */
void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq[5]);
/* Memory access layer */
void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
/* PowerPC 405 microcontrollers */
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,

153
hw/ppc405_uc.c
View File

@ -164,7 +164,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
void ppc4xx_plb_init (CPUState *env)
static void ppc4xx_plb_init(CPUState *env)
{
ppc4xx_plb_t *plb;
@ -241,7 +241,7 @@ static void ppc4xx_pob_reset (void *opaque)
pob->besr[1] = 0x0000000;
}
void ppc4xx_pob_init (CPUState *env)
static void ppc4xx_pob_init(CPUState *env)
{
ppc4xx_pob_t *pob;
@ -250,14 +250,13 @@ void ppc4xx_pob_init (CPUState *env)
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
ppc4xx_pob_reset(env);
ppc4xx_pob_reset(pob);
}
/*****************************************************************************/
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
target_phys_addr_t base;
uint8_t cr;
uint8_t pr;
};
@ -271,7 +270,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
opba = opaque;
switch (addr - opba->base) {
switch (addr) {
case 0x00:
ret = opba->cr;
break;
@ -295,7 +294,7 @@ static void opba_writeb (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
opba = opaque;
switch (addr - opba->base) {
switch (addr) {
case 0x00:
opba->cr = value & 0xF8;
break;
@ -374,20 +373,19 @@ static void ppc4xx_opba_reset (void *opaque)
opba->pr = 0x11;
}
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset)
static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
int io;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
opba->base = offset;
#ifdef DEBUG_OPBA
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, base);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x002,
opba_read, opba_write, opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
io = cpu_register_io_memory(opba_read, opba_write, opba);
cpu_register_physical_memory(base, 0x002, io);
ppc4xx_opba_reset(opba);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
/*****************************************************************************/
@ -574,7 +572,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
void ppc405_ebc_init (CPUState *env)
static void ppc405_ebc_init(CPUState *env)
{
ppc4xx_ebc_t *ebc;
@ -665,7 +663,7 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
{
ppc405_dma_t *dma;
@ -727,7 +725,6 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
target_phys_addr_t base;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
@ -829,48 +826,19 @@ static void ppc405_gpio_reset (void *opaque)
gpio = opaque;
}
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset)
static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
int io;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
gpio->base = offset;
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
cpu_register_physical_memory(base, 0x038, io);
ppc405_gpio_reset(gpio);
qemu_register_reset(&ppc405_gpio_reset, gpio);
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x038,
ppc405_gpio_read, ppc405_gpio_write, gpio);
}
/*****************************************************************************/
/* Serial ports */
static CPUReadMemoryFunc *serial_mm_read[] = {
&serial_mm_readb,
&serial_mm_readw,
&serial_mm_readl,
};
static CPUWriteMemoryFunc *serial_mm_write[] = {
&serial_mm_writeb,
&serial_mm_writew,
&serial_mm_writel,
};
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq,
CharDriverState *chr)
{
void *serial;
#ifdef DEBUG_SERIAL
printf("%s: offset " PADDRX "\n", __func__, offset);
#endif
serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
ppc4xx_mmio_register(env, mmio, offset, 0x008,
serial_mm_read, serial_mm_write, serial);
}
/*****************************************************************************/
@ -1021,7 +989,7 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
void ppc405_ocm_init (CPUState *env)
static void ppc405_ocm_init(CPUState *env)
{
ppc405_ocm_t *ocm;
@ -1043,7 +1011,6 @@ void ppc405_ocm_init (CPUState *env)
/* I2C controller */
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
target_phys_addr_t base;
qemu_irq irq;
uint8_t mdata;
uint8_t lmadr;
@ -1071,7 +1038,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
i2c = opaque;
switch (addr - i2c->base) {
switch (addr) {
case 0x00:
// i2c_readbyte(&i2c->mdata);
ret = i2c->mdata;
@ -1138,7 +1105,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
i2c = opaque;
switch (addr - i2c->base) {
switch (addr) {
case 0x00:
i2c->mdata = value;
// i2c_sendbyte(&i2c->mdata);
@ -1266,20 +1233,19 @@ static void ppc4xx_i2c_reset (void *opaque)
i2c->directcntl = 0x0F;
}
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq)
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
int io;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->base = offset;
i2c->irq = irq;
ppc4xx_i2c_reset(i2c);
#ifdef DEBUG_I2C
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, base);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x011,
i2c_read, i2c_write, i2c);
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
cpu_register_physical_memory(base, 0x011, io);
ppc4xx_i2c_reset(i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@ -1287,7 +1253,6 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
target_phys_addr_t base;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
@ -1399,7 +1364,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
gpt = opaque;
switch (addr - gpt->base) {
switch (addr) {
case 0x00:
/* Time base counter */
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
@ -1428,12 +1393,12 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
break;
case 0x80 ... 0x90:
/* Compare timer */
idx = ((addr - gpt->base) - 0x80) >> 2;
idx = (addr - 0x80) >> 2;
ret = gpt->comp[idx];
break;
case 0xC0 ... 0xD0:
/* Compare mask */
idx = ((addr - gpt->base) - 0xC0) >> 2;
idx = (addr - 0xC0) >> 2;
ret = gpt->mask[idx];
break;
default:
@ -1454,7 +1419,7 @@ static void ppc4xx_gpt_writel (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
gpt = opaque;
switch (addr - gpt->base) {
switch (addr) {
case 0x00:
/* Time base counter */
gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
@ -1492,13 +1457,13 @@ static void ppc4xx_gpt_writel (void *opaque,
break;
case 0x80 ... 0x90:
/* Compare timer */
idx = ((addr - gpt->base) - 0x80) >> 2;
idx = (addr - 0x80) >> 2;
gpt->comp[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
case 0xC0 ... 0xD0:
/* Compare mask */
idx = ((addr - gpt->base) - 0xC0) >> 2;
idx = (addr - 0xC0) >> 2;
gpt->mask[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
@ -1545,24 +1510,24 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irqs[5])
static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
int io;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
gpt->base = offset;
for (i = 0; i < 5; i++)
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
ppc4xx_gpt_reset(gpt);
#ifdef DEBUG_GPT
printf("%s: offset " PADDRX "\n", __func__, offset);
printf("%s: offset " PADDRX "\n", __func__, base);
#endif
ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
gpt_read, gpt_write, gpt);
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
ppc4xx_gpt_reset(gpt);
}
/*****************************************************************************/
@ -1778,7 +1743,7 @@ static void ppc40x_mal_reset (void *opaque)
mal->txeobisr = 0x00000000;
}
void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;
@ -2183,20 +2148,18 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
CPUState *env;
ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
&clk_setup[PPC405CR_TMR_CLK], sysclk);
/* Memory mapped devices registers */
mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(env, mmio, 0x600);
ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
@ -2217,15 +2180,17 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
}
if (serial_hds[1] != NULL) {
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
}
/* IIC controller */
ppc405_i2c_init(env, mmio, 0x500, pic[2]);
ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
ppc405_gpio_init(env, mmio, 0x700);
ppc405_gpio_init(0xef600700);
/* CPU control */
ppc405cr_cpc_init(env, clk_setup, sysclk);
@ -2528,7 +2493,6 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUState *env;
ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
@ -2539,13 +2503,12 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
/* Internal devices init */
/* Memory mapped devices registers */
mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(env, mmio, 0x600);
ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
@ -2566,15 +2529,17 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
dma_irqs[3] = pic[8];
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
ppc405_i2c_init(env, mmio, 0x500, pic[2]);
ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
ppc405_gpio_init(env, mmio, 0x700);
ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hds[0] != NULL) {
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
}
if (serial_hds[1] != NULL) {
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
}
/* OCM */
ppc405_ocm_init(env);
@ -2584,7 +2549,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
gpt_irqs[2] = pic[21];
gpt_irqs[3] = pic[22];
gpt_irqs[4] = pic[23];
ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
ppc4xx_gpt_init(0xef600000, gpt_irqs);
/* PCI */
/* Uses pic[3], pic[16], pic[18] */
/* MAL */

18
hw/ppc440.c
View File

@ -12,6 +12,7 @@
*/
#include "hw.h"
#include "pc.h"
#include "isa.h"
#include "ppc.h"
#include "ppc4xx.h"
@ -40,7 +41,6 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
ppc4xx_mmio_t *mmio;
qemu_irq *pic;
qemu_irq *irqs;
qemu_irq *pci_irqs;
@ -87,14 +87,14 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
/* MMIO -- most "miscellaneous" devices live above 0xef600000. */
mmio = ppc4xx_mmio_init(env, 0xef600000);
if (serial_hds[0])
ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
if (serial_hds[1])
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
}
return env;
}

7
hw/ppc4xx.h
View File

@ -32,13 +32,6 @@ CPUState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk);
typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, uint32_t len,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write, void *opaque);
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
/* PowerPC 4xx universal interrupt controller */
enum {
PPCUIC_OUTPUT_INT = 0,

195
hw/ppc4xx_devs.c
View File

@ -65,201 +65,6 @@ CPUState *ppc4xx_init (const char *cpu_model,
return env;
}
/*****************************************************************************/
/* Fake device used to map multiple devices in a single memory page */
#define MMIO_AREA_BITS 8
#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
struct ppc4xx_mmio_t {
target_phys_addr_t base;
CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
void *opaque[MMIO_AREA_NB];
};
static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
ppc4xx_mmio_t *mmio;
mmio = opaque;
printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
addr, mmio->base);
#endif
return 0;
}
static void unassigned_mmio_writeb (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
ppc4xx_mmio_t *mmio;
mmio = opaque;
printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
addr, val, mmio->base);
#endif
}
static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
unassigned_mmio_readb,
unassigned_mmio_readb,
unassigned_mmio_readb,
};
static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
unassigned_mmio_writeb,
unassigned_mmio_writeb,
unassigned_mmio_writeb,
};
static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
target_phys_addr_t addr, int len)
{
CPUReadMemoryFunc **mem_read;
uint32_t ret;
int idx;
idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
mmio, len, addr, idx);
#endif
mem_read = mmio->mem_read[idx];
ret = (*mem_read[len])(mmio->opaque[idx], addr);
return ret;
}
static void mmio_writelen (ppc4xx_mmio_t *mmio,
target_phys_addr_t addr, uint32_t value, int len)
{
CPUWriteMemoryFunc **mem_write;
int idx;
idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
__func__, mmio, len, addr, idx, value);
#endif
mem_write = mmio->mem_write[idx];
(*mem_write[len])(mmio->opaque[idx], addr, value);
}
static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
return mmio_readlen(opaque, addr, 0);
}
static void mmio_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
mmio_writelen(opaque, addr, value, 0);
}
static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
return mmio_readlen(opaque, addr, 1);
}
static void mmio_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
mmio_writelen(opaque, addr, value, 1);
}
static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
return mmio_readlen(opaque, addr, 2);
}
static void mmio_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
mmio_writelen(opaque, addr, value, 2);
}
static CPUReadMemoryFunc *mmio_read[] = {
&mmio_readb,
&mmio_readw,
&mmio_readl,
};
static CPUWriteMemoryFunc *mmio_write[] = {
&mmio_writeb,
&mmio_writew,
&mmio_writel,
};
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, uint32_t len,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write, void *opaque)
{
target_phys_addr_t end;
int idx, eidx;
if ((offset + len) > TARGET_PAGE_SIZE)
return -1;
idx = MMIO_IDX(offset);
end = offset + len - 1;
eidx = MMIO_IDX(end);
#if defined(DEBUG_MMIO)
printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
__func__, offset, len, end, idx, eidx);
#endif
for (; idx <= eidx; idx++) {
mmio->mem_read[idx] = mem_read;
mmio->mem_write[idx] = mem_write;
mmio->opaque[idx] = opaque;
}
return 0;
}
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
{
ppc4xx_mmio_t *mmio;
int mmio_memory;
mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
mmio->base = base;
mmio_memory = cpu_register_io_memory(mmio_read, mmio_write, mmio);
#if defined(DEBUG_MMIO)
printf("%s: base " PADDRX " len %08x %d\n", __func__,
base, TARGET_PAGE_SIZE, mmio_memory);
#endif
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
unassigned_mmio_read, unassigned_mmio_write,
mmio);
return mmio;
}
/*****************************************************************************/
/* "Universal" Interrupt controller */
enum {

18
hw/serial.c
View File

@ -745,22 +745,22 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
}
/* Memory mapped interface */
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
}
void serial_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
@ -772,8 +772,8 @@ uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
return val;
}
void serial_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@ -782,7 +782,7 @@ void serial_mm_writew (void *opaque,
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
@ -794,8 +794,8 @@ uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
return val;
}
void serial_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN