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target/arm: Convert Table Branch

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:30 -07:00 committed by Peter Maydell
parent 610f4e1764
commit 808092bbe3
2 changed files with 41 additions and 24 deletions
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8
target/arm/t32.decode
View File

@ -489,7 +489,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
# Load/Store Exclusive and Load-Acquire/Store-Release
# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch
@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \
&strex rt2=15 imm=%imm8x4
@ -533,6 +533,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
&tbranch rn rm
@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch
TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch
TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch
# Parallel addition and subtraction
SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm

57
target/arm/translate.c
View File

@ -10081,6 +10081,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
return true;
}
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
{
TCGv_i32 addr, tmp;
tmp = load_reg(s, a->rm);
if (half) {
tcg_gen_add_i32(tmp, tmp, tmp);
}
addr = load_reg(s, a->rn);
tcg_gen_add_i32(addr, addr, tmp);
gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
half ? MO_UW | s->be_data : MO_UB);
tcg_temp_free_i32(addr);
tcg_gen_add_i32(tmp, tmp, tmp);
tcg_gen_addi_i32(tmp, tmp, read_pc(s));
store_reg(s, 15, tmp);
return true;
}
static bool trans_TBB(DisasContext *s, arg_tbranch *a)
{
return op_tbranch(s, a, false);
}
static bool trans_TBH(DisasContext *s, arg_tbranch *a)
{
return op_tbranch(s, a, true);
}
/*
* Supervisor call
*/
@ -10466,9 +10497,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
uint32_t rd, rn, rm, rs;
TCGv_i32 tmp;
TCGv_i32 addr;
uint32_t rd, rn, rs;
int op;
/*
@ -10514,7 +10543,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;
rm = insn & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
@ -10587,25 +10615,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Load/store exclusive, in decodetree */
goto illegal_op;
} else if ((insn & (7 << 5)) == 0) {
/* Table Branch. */
addr = load_reg(s, rn);
tmp = load_reg(s, rm);
tcg_gen_add_i32(addr, addr, tmp);
if (insn & (1 << 4)) {
/* tbh */
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
} else { /* tbb */
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
}
tcg_temp_free_i32(addr);
tcg_gen_shli_i32(tmp, tmp, 1);
tcg_gen_addi_i32(tmp, tmp, read_pc(s));
store_reg(s, 15, tmp);
/* Table Branch, in decodetree */
goto illegal_op;
} else {
/* Load/store exclusive, load-acq/store-rel, in decodetree */
goto illegal_op;