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target-i386: use inverted setcond when computing NS or NZ
Make gen_compute_eflags_z and gen_compute_eflags_s able to compute the inverted condition, and use this in gen_setcc_slow_T0. We cannot do it yet in gen_compute_eflags_c, but prepare the code for it anyway. It is not worthwhile for PF, as usual. shr+and+xor could be replaced by and+setcond. I'm not doing it yet. Reviewed-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
086c407784
commit
8115f11735
@ -870,11 +870,14 @@ static void gen_op_update_neg_cc(void)
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}
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/* compute eflags.C to reg */
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static void gen_compute_eflags_c(DisasContext *s, TCGv reg)
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static void gen_compute_eflags_c(DisasContext *s, TCGv reg, bool inv)
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{
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gen_update_cc_op(s);
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gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
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tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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}
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}
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/* compute all eflags to cc_src */
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@ -898,7 +901,7 @@ static void gen_compute_eflags_p(DisasContext *s, TCGv reg)
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}
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/* compute eflags.S to reg */
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static void gen_compute_eflags_s(DisasContext *s, TCGv reg)
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static void gen_compute_eflags_s(DisasContext *s, TCGv reg, bool inv)
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{
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switch (s->cc_op) {
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case CC_OP_DYNAMIC:
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@ -907,12 +910,15 @@ static void gen_compute_eflags_s(DisasContext *s, TCGv reg)
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case CC_OP_EFLAGS:
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tcg_gen_shri_tl(reg, cpu_cc_src, 7);
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tcg_gen_andi_tl(reg, reg, 1);
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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}
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break;
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default:
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{
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int size = (s->cc_op - CC_OP_ADDB) & 3;
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TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
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tcg_gen_setcondi_tl(TCG_COND_LT, reg, t0, 0);
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tcg_gen_setcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, reg, t0, 0);
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}
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break;
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}
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@ -927,7 +933,7 @@ static void gen_compute_eflags_o(DisasContext *s, TCGv reg)
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}
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/* compute eflags.Z to reg */
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static void gen_compute_eflags_z(DisasContext *s, TCGv reg)
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static void gen_compute_eflags_z(DisasContext *s, TCGv reg, bool inv)
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{
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switch (s->cc_op) {
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case CC_OP_DYNAMIC:
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@ -936,27 +942,33 @@ static void gen_compute_eflags_z(DisasContext *s, TCGv reg)
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case CC_OP_EFLAGS:
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tcg_gen_shri_tl(reg, cpu_cc_src, 6);
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tcg_gen_andi_tl(reg, reg, 1);
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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}
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break;
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default:
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{
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int size = (s->cc_op - CC_OP_ADDB) & 3;
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TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
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tcg_gen_setcondi_tl(TCG_COND_EQ, reg, t0, 0);
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tcg_gen_setcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, reg, t0, 0);
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}
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break;
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}
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}
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static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
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static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op, bool inv)
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{
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switch(jcc_op) {
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case JCC_O:
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gen_compute_eflags_o(s, cpu_T[0]);
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break;
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case JCC_B:
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gen_compute_eflags_c(s, cpu_T[0]);
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gen_compute_eflags_c(s, cpu_T[0], inv);
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inv = false;
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break;
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case JCC_Z:
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gen_compute_eflags_z(s, cpu_T[0]);
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gen_compute_eflags_z(s, cpu_T[0], inv);
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inv = false;
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break;
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case JCC_BE:
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gen_compute_eflags(s);
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@ -965,7 +977,8 @@ static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
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break;
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case JCC_S:
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gen_compute_eflags_s(s, cpu_T[0]);
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gen_compute_eflags_s(s, cpu_T[0], inv);
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inv = false;
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break;
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case JCC_P:
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gen_compute_eflags_p(s, cpu_T[0]);
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@ -988,6 +1001,9 @@ static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
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break;
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}
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if (inv) {
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tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
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}
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}
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/* return true if setcc_slow is not needed (WARNING: must be kept in
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@ -1153,7 +1169,7 @@ static inline void gen_jcc1(DisasContext *s, int b, int l1)
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break;
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default:
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slow_jcc:
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gen_setcc_slow_T0(s, jcc_op);
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gen_setcc_slow_T0(s, jcc_op, false);
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tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
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cpu_T[0], 0, l1);
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break;
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@ -1367,7 +1383,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
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}
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switch(op) {
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case OP_ADCL:
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gen_compute_eflags_c(s1, cpu_tmp4);
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gen_compute_eflags_c(s1, cpu_tmp4, false);
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
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if (d != OR_TMP0)
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@ -1382,7 +1398,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d)
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set_cc_op(s1, CC_OP_DYNAMIC);
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break;
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case OP_SBBL:
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gen_compute_eflags_c(s1, cpu_tmp4);
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gen_compute_eflags_c(s1, cpu_tmp4, false);
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tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
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if (d != OR_TMP0)
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@ -1456,7 +1472,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c)
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gen_op_mov_TN_reg(ot, 0, d);
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else
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gen_op_ld_T0_A0(ot + s1->mem_index);
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gen_compute_eflags_c(s1, cpu_cc_src);
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gen_compute_eflags_c(s1, cpu_cc_src, false);
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if (c > 0) {
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tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
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set_cc_op(s1, CC_OP_INCB + ot);
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@ -2407,10 +2423,7 @@ static void gen_setcc(DisasContext *s, int b)
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worth to */
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inv = b & 1;
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jcc_op = (b >> 1) & 7;
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gen_setcc_slow_T0(s, jcc_op);
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if (inv) {
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tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
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}
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gen_setcc_slow_T0(s, jcc_op, inv);
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}
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}
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@ -6881,7 +6894,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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case 0xd6: /* salc */
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if (CODE64(s))
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goto illegal_op;
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gen_compute_eflags_c(s, cpu_T[0]);
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gen_compute_eflags_c(s, cpu_T[0], false);
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tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
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gen_op_mov_reg_T0(OT_BYTE, R_EAX);
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break;
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