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Clean up PowerPC SLB handling code

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Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'.  While the layout in these fields does match the
description of the SLB in the architecture document, it is not
convenient either for looking up the SLB, or for emulating the
slbmte instruction.

This patch, therefore, reorganizes the SLB entry structure to be
divided in the the "ESID related" and "VSID related" fields as
they are divided in instructions accessing the SLB.

In addition to making the code smaller and more readable, this will
make it easier to implement for the 1TB segments used in more
recent PowerPC chips.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson 2011-04-01 15:15:08 +11:00 committed by Alexander Graf
parent 17d9b3af5b
commit 81762d6dd0
4 changed files with 85 additions and 142 deletions
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29
target-ppc/cpu.h
View File

@ -43,6 +43,8 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 64 # define TARGET_VIRT_ADDR_SPACE_BITS 64
#endif #endif
#define TARGET_PAGE_BITS_16M 24
#else /* defined (TARGET_PPC64) */ #else /* defined (TARGET_PPC64) */
/* PowerPC 32 definitions */ /* PowerPC 32 definitions */
#define TARGET_LONG_BITS 32 #define TARGET_LONG_BITS 32
@ -359,10 +361,31 @@ union ppc_tlb_t {
typedef struct ppc_slb_t ppc_slb_t; typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t { struct ppc_slb_t {
uint64_t tmp64; uint64_t esid;
uint32_t tmp; uint64_t vsid;
}; };
/* Bits in the SLB ESID word */
#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
#define SLB_ESID_V 0x0000000008000000ULL /* valid */
/* Bits in the SLB VSID word */
#define SLB_VSID_SHIFT 12
#define SLB_VSID_SSIZE_SHIFT 62
#define SLB_VSID_B 0xc000000000000000ULL
#define SLB_VSID_B_256M 0x0000000000000000ULL
#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
#define SLB_VSID_KS 0x0000000000000800ULL
#define SLB_VSID_KP 0x0000000000000400ULL
#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
#define SLB_VSID_L 0x0000000000000100ULL
#define SLB_VSID_C 0x0000000000000080ULL /* class */
#define SLB_VSID_LP 0x0000000000000030ULL
#define SLB_VSID_ATTR 0x0000000000000FFFULL
#define SEGMENT_SHIFT_256M 28
#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
/*****************************************************************************/ /*****************************************************************************/
/* Machine state register bits definition */ /* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */
@ -755,7 +778,7 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
void ppc_store_asr (CPUPPCState *env, target_ulong value); void ppc_store_asr (CPUPPCState *env, target_ulong value);
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr); target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr); target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value); void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */ #endif /* !defined(CONFIG_USER_ONLY) */

188
target-ppc/helper.c
View File

@ -672,85 +672,36 @@ static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
{
ppc_slb_t *retval = &env->slb[nr];
#if 0 // XXX implement bridge mode?
if (env->spr[SPR_ASR] & 1) {
target_phys_addr_t sr_base;
sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
sr_base += (12 * nr);
retval->tmp64 = ldq_phys(sr_base);
retval->tmp = ldl_phys(sr_base + 8);
}
#endif
return retval;
}
static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
{
ppc_slb_t *entry = &env->slb[nr];
if (slb == entry)
return;
entry->tmp64 = slb->tmp64;
entry->tmp = slb->tmp;
}
static inline int slb_is_valid(ppc_slb_t *slb)
{
return (int)(slb->tmp64 & 0x0000000008000000ULL);
}
static inline void slb_invalidate(ppc_slb_t *slb)
{
slb->tmp64 &= ~0x0000000008000000ULL;
}
static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
target_ulong *vsid, target_ulong *page_mask, target_ulong *vsid, target_ulong *page_mask,
int *attr, int *target_page_bits) int *attr, int *target_page_bits)
{ {
target_ulong mask; uint64_t esid;
int n, ret; int n;
ret = -5;
LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
mask = 0x0000000000000000ULL; /* Avoid gcc warning */
for (n = 0; n < env->slb_nr; n++) {
ppc_slb_t *slb = slb_get_entry(env, n);
LOG_SLB("%s: seg %d %016" PRIx64 " %08" esid = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
if (slb_is_valid(slb)) { for (n = 0; n < env->slb_nr; n++) {
/* SLB entry is valid */ ppc_slb_t *slb = &env->slb[n];
mask = 0xFFFFFFFFF0000000ULL;
if (slb->tmp & 0x8) { LOG_SLB("%s: slot %d %016" PRIx64 " %016"
/* 16 MB PTEs */ PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
if (target_page_bits) if (slb->esid == esid) {
*target_page_bits = 24; *vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
} else { *page_mask = ~SEGMENT_MASK_256M;
/* 4 KB PTEs */ *attr = slb->vsid & SLB_VSID_ATTR;
if (target_page_bits) if (target_page_bits) {
*target_page_bits = TARGET_PAGE_BITS; *target_page_bits = (slb->vsid & SLB_VSID_L)
} ? TARGET_PAGE_BITS_16M
if ((eaddr & mask) == (slb->tmp64 & mask)) { : TARGET_PAGE_BITS;
/* SLB match */
*vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
*page_mask = ~mask;
*attr = slb->tmp & 0xFF;
ret = n;
break;
} }
return n;
} }
} }
return ret; return -5;
} }
void ppc_slb_invalidate_all (CPUPPCState *env) void ppc_slb_invalidate_all (CPUPPCState *env)
@ -760,11 +711,10 @@ void ppc_slb_invalidate_all (CPUPPCState *env)
do_invalidate = 0; do_invalidate = 0;
/* XXX: Warning: slbia never invalidates the first segment */ /* XXX: Warning: slbia never invalidates the first segment */
for (n = 1; n < env->slb_nr; n++) { for (n = 1; n < env->slb_nr; n++) {
ppc_slb_t *slb = slb_get_entry(env, n); ppc_slb_t *slb = &env->slb[n];
if (slb_is_valid(slb)) { if (slb->esid & SLB_ESID_V) {
slb_invalidate(slb); slb->esid &= ~SLB_ESID_V;
slb_set_entry(env, n, slb);
/* XXX: given the fact that segment size is 256 MB or 1TB, /* XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask) * and we still don't have a tlb_flush_mask(env, n, mask)
* in Qemu, we just invalidate all TLBs * in Qemu, we just invalidate all TLBs
@ -781,68 +731,44 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
target_ulong vsid, page_mask; target_ulong vsid, page_mask;
int attr; int attr;
int n; int n;
n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
if (n >= 0) {
ppc_slb_t *slb = slb_get_entry(env, n);
if (slb_is_valid(slb)) {
slb_invalidate(slb);
slb_set_entry(env, n, slb);
/* XXX: given the fact that segment size is 256 MB or 1TB,
* and we still don't have a tlb_flush_mask(env, n, mask)
* in Qemu, we just invalidate all TLBs
*/
tlb_flush(env, 1);
}
}
}
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
{
target_ulong rt;
ppc_slb_t *slb = slb_get_entry(env, slb_nr);
if (slb_is_valid(slb)) {
/* SLB entry is valid */
/* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
rt = slb->tmp >> 8; /* 65:88 => 40:63 */
rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
/* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
rt |= ((slb->tmp >> 4) & 0xF) << 27;
} else {
rt = 0;
}
LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
return rt;
}
void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
{
ppc_slb_t *slb; ppc_slb_t *slb;
uint64_t vsid; n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
uint64_t esid; if (n < 0) {
int flags, valid, slb_nr; return;
}
vsid = rs >> 12; slb = &env->slb[n];
flags = ((rs >> 8) & 0xf);
esid = rb >> 28; if (slb->esid & SLB_ESID_V) {
valid = (rb & (1 << 27)); slb->esid &= ~SLB_ESID_V;
slb_nr = rb & 0xfff;
slb = slb_get_entry(env, slb_nr); /* XXX: given the fact that segment size is 256 MB or 1TB,
slb->tmp64 = (esid << 28) | valid | (vsid >> 24); * and we still don't have a tlb_flush_mask(env, n, mask)
slb->tmp = (vsid << 8) | (flags << 3); * in Qemu, we just invalidate all TLBs
*/
tlb_flush(env, 1);
}
}
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
{
int slot = rb & 0xfff;
uint64_t esid = rb & ~0xfff;
ppc_slb_t *slb = &env->slb[slot];
if (slot >= env->slb_nr) {
return -1;
}
slb->esid = esid;
slb->vsid = rs;
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
" %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64, " %016" PRIx64 "\n", __func__, slot, rb, rs,
slb->tmp); slb->esid, slb->vsid);
slb_set_entry(env, slb_nr, slb); return 0;
} }
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
@ -860,24 +786,22 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
{ {
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
target_ulong sr, vsid, vsid_mask, pgidx, page_mask; target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
#if defined(TARGET_PPC64)
int attr;
#endif
int ds, vsid_sh, sdr_sh, pr, target_page_bits; int ds, vsid_sh, sdr_sh, pr, target_page_bits;
int ret, ret2; int ret, ret2;
pr = msr_pr; pr = msr_pr;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) { if (env->mmu_model & POWERPC_MMU_64) {
int attr;
LOG_MMU("Check SLBs\n"); LOG_MMU("Check SLBs\n");
ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
&target_page_bits); &target_page_bits);
if (ret < 0) if (ret < 0)
return ret; return ret;
ctx->key = ((attr & 0x40) && (pr != 0)) || ctx->key = !!(pr ? (attr & SLB_VSID_KP) : (attr & SLB_VSID_KS));
((attr & 0x80) && (pr == 0)) ? 1 : 0;
ds = 0; ds = 0;
ctx->nx = attr & 0x10 ? 1 : 0; ctx->nx = !!(attr & SLB_VSID_N);
ctx->eaddr = eaddr; ctx->eaddr = eaddr;
vsid_mask = 0x00003FFFFFFFFF80ULL; vsid_mask = 0x00003FFFFFFFFF80ULL;
vsid_sh = 7; vsid_sh = 7;

1
target-ppc/helper.h
View File

@ -340,7 +340,6 @@ DEF_HELPER_1(74xx_tlbi, void, tl)
DEF_HELPER_FLAGS_0(tlbia, TCG_CALL_CONST, void) DEF_HELPER_FLAGS_0(tlbia, TCG_CALL_CONST, void)
DEF_HELPER_FLAGS_1(tlbie, TCG_CALL_CONST, void, tl) DEF_HELPER_FLAGS_1(tlbie, TCG_CALL_CONST, void, tl)
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(load_slb, TCG_CALL_CONST, tl, tl)
DEF_HELPER_FLAGS_2(store_slb, TCG_CALL_CONST, void, tl, tl) DEF_HELPER_FLAGS_2(store_slb, TCG_CALL_CONST, void, tl, tl)
DEF_HELPER_FLAGS_0(slbia, TCG_CALL_CONST, void) DEF_HELPER_FLAGS_0(slbia, TCG_CALL_CONST, void)
DEF_HELPER_FLAGS_1(slbie, TCG_CALL_CONST, void, tl) DEF_HELPER_FLAGS_1(slbie, TCG_CALL_CONST, void, tl)

9
target-ppc/op_helper.c
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@ -3746,14 +3746,11 @@ void helper_store_sr (target_ulong sr_num, target_ulong val)
/* SLB management */ /* SLB management */
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
target_ulong helper_load_slb (target_ulong slb_nr)
{
return ppc_load_slb(env, slb_nr);
}
void helper_store_slb (target_ulong rb, target_ulong rs) void helper_store_slb (target_ulong rb, target_ulong rs)
{ {
ppc_store_slb(env, rb, rs); if (ppc_store_slb(env, rb, rs) < 0) {
helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL);
}
} }
void helper_slbia (void) void helper_slbia (void)