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tcg: Clean up from 'next_tb'
The value returned from tcg_qemu_tb_exec() is the value passed to the corresponding tcg_gen_exit_tb() at translation time of the last TB attempted to execute. It is a little confusing to store it in a variable named 'next_tb'. In fact, it is a combination of 4-byte aligned pointer and additional information in its two least significant bits. Break it down right away into two variables named 'last_tb' and 'tb_exit' which are a pointer to the last TB attempted to execute and the TB exit reason, correspondingly. This simplifies the code and improves its readability. Correct a misleading documentation comment for tcg_qemu_tb_exec() and fix logging in cpu_tb_exec(). Also rename a misleading 'next_tb' in another couple of places. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
7687bf52e5
commit
819af24b9c
59
cpu-exec.c
59
cpu-exec.c
@ -136,7 +136,9 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
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static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
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{
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CPUArchState *env = cpu->env_ptr;
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uintptr_t next_tb;
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uintptr_t ret;
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TranslationBlock *last_tb;
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int tb_exit;
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uint8_t *tb_ptr = itb->tc_ptr;
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qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
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@ -160,36 +162,37 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
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#endif /* DEBUG_DISAS */
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cpu->can_do_io = !use_icount;
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next_tb = tcg_qemu_tb_exec(env, tb_ptr);
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ret = tcg_qemu_tb_exec(env, tb_ptr);
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cpu->can_do_io = 1;
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trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
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next_tb & TB_EXIT_MASK);
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last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK);
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tb_exit = ret & TB_EXIT_MASK;
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trace_exec_tb_exit(last_tb, tb_exit);
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if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
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if (tb_exit > TB_EXIT_IDX1) {
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/* We didn't start executing this TB (eg because the instruction
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* counter hit zero); we must restore the guest PC to the address
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* of the start of the TB.
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*/
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CPUClass *cc = CPU_GET_CLASS(cpu);
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TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
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qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
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qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
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"Stopped execution of TB chain before %p ["
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TARGET_FMT_lx "] %s\n",
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itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
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last_tb->tc_ptr, last_tb->pc,
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lookup_symbol(last_tb->pc));
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if (cc->synchronize_from_tb) {
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cc->synchronize_from_tb(cpu, tb);
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cc->synchronize_from_tb(cpu, last_tb);
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} else {
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assert(cc->set_pc);
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cc->set_pc(cpu, tb->pc);
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cc->set_pc(cpu, last_tb->pc);
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}
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}
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if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
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if (tb_exit == TB_EXIT_REQUESTED) {
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/* We were asked to stop executing TBs (probably a pending
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* interrupt. We've now stopped, so clear the flag.
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*/
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cpu->tcg_exit_req = 0;
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}
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return next_tb;
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return ret;
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}
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#ifndef CONFIG_USER_ONLY
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@ -358,8 +361,8 @@ int cpu_exec(CPUState *cpu)
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CPUArchState *env = &x86_cpu->env;
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#endif
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int ret, interrupt_request;
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TranslationBlock *tb;
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uintptr_t next_tb;
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TranslationBlock *tb, *last_tb;
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int tb_exit = 0;
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SyncClocks sc;
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/* replay_interrupt may need current_cpu */
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@ -442,7 +445,7 @@ int cpu_exec(CPUState *cpu)
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#endif
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}
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next_tb = 0; /* force lookup of first TB */
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last_tb = NULL; /* forget the last executed TB after exception */
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for(;;) {
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interrupt_request = cpu->interrupt_request;
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if (unlikely(interrupt_request)) {
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@ -487,7 +490,7 @@ int cpu_exec(CPUState *cpu)
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else {
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replay_interrupt();
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if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
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next_tb = 0;
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last_tb = NULL;
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}
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}
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/* Don't use the cached interrupt_request value,
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@ -496,7 +499,7 @@ int cpu_exec(CPUState *cpu)
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cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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next_tb = 0;
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last_tb = NULL;
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}
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}
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if (unlikely(cpu->exit_request
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@ -513,22 +516,24 @@ int cpu_exec(CPUState *cpu)
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/* as some TB could have been invalidated because
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of memory exceptions while generating the code, we
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must recompute the hash index here */
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next_tb = 0;
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last_tb = NULL;
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tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
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}
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/* See if we can patch the calling TB. */
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if (next_tb != 0 && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
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tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
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next_tb & TB_EXIT_MASK, tb);
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if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
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tb_add_jump(last_tb, tb_exit, tb);
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}
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tb_unlock();
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if (likely(!cpu->exit_request)) {
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uintptr_t ret;
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trace_exec_tb(tb, tb->pc);
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/* execute the generated code */
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cpu->current_tb = tb;
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next_tb = cpu_tb_exec(cpu, tb);
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ret = cpu_tb_exec(cpu, tb);
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cpu->current_tb = NULL;
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switch (next_tb & TB_EXIT_MASK) {
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last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK);
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tb_exit = ret & TB_EXIT_MASK;
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switch (tb_exit) {
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case TB_EXIT_REQUESTED:
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/* Something asked us to stop executing
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* chained TBs; just continue round the main
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@ -541,7 +546,7 @@ int cpu_exec(CPUState *cpu)
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* or cpu->interrupt_request.
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*/
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smp_rmb();
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next_tb = 0;
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last_tb = NULL;
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break;
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case TB_EXIT_ICOUNT_EXPIRED:
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{
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@ -559,12 +564,12 @@ int cpu_exec(CPUState *cpu)
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} else {
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if (insns_left > 0) {
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/* Execute remaining instructions. */
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tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
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cpu_exec_nocache(cpu, insns_left, tb, false);
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cpu_exec_nocache(cpu, insns_left,
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last_tb, false);
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align_clocks(&sc, cpu);
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}
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cpu->exception_index = EXCP_INTERRUPT;
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next_tb = 0;
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last_tb = NULL;
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cpu_loop_exit(cpu);
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}
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break;
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19
tcg/tcg.h
19
tcg/tcg.h
@ -925,7 +925,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
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/**
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* tcg_qemu_tb_exec:
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* @env: CPUArchState * for the CPU
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* @env: pointer to CPUArchState for the CPU
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* @tb_ptr: address of generated code for the TB to execute
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*
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* Start executing code from a given translation block.
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@ -936,30 +936,31 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
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* which has not yet been directly linked, or an asynchronous
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* event such as an interrupt needs handling.
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*
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* The return value is a pointer to the next TB to execute
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* (if known; otherwise zero). This pointer is assumed to be
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* 4-aligned, and the bottom two bits are used to return further
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* information:
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* Return: The return value is the value passed to the corresponding
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* tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
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* The value is either zero or a 4-byte aligned pointer to that TB combined
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* with additional information in its two least significant bits. The
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* additional information is encoded as follows:
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* 0, 1: the link between this TB and the next is via the specified
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* TB index (0 or 1). That is, we left the TB via (the equivalent
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* of) "goto_tb <index>". The main loop uses this to determine
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* how to link the TB just executed to the next.
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* 2: we are using instruction counting code generation, and we
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* did not start executing this TB because the instruction counter
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* would hit zero midway through it. In this case the next-TB pointer
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* would hit zero midway through it. In this case the pointer
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* returned is the TB we were about to execute, and the caller must
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* arrange to execute the remaining count of instructions.
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* 3: we stopped because the CPU's exit_request flag was set
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* (usually meaning that there is an interrupt that needs to be
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* handled). The next-TB pointer returned is the TB we were
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* about to execute when we noticed the pending exit request.
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* handled). The pointer returned is the TB we were about to execute
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* when we noticed the pending exit request.
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*
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* If the bottom two bits indicate an exit-via-index then the CPU
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* state is correctly synchronised and ready for execution of the next
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* TB (and in particular the guest PC is the address to execute next).
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* Otherwise, we gave up on execution of this TB before it started, and
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* the caller must fix up the CPU state by calling the CPU's
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* synchronize_from_tb() method with the next-TB pointer we return (falling
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* synchronize_from_tb() method with the TB pointer we return (falling
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* back to calling the CPU's set_pc method with tb->pb if no
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* synchronize_from_tb() method exists).
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*
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6
tci.c
6
tci.c
@ -467,7 +467,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
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{
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long tcg_temps[CPU_TEMP_BUF_NLONGS];
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uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
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uintptr_t next_tb = 0;
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uintptr_t ret = 0;
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tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
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tci_reg[TCG_REG_CALL_STACK] = sp_value;
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@ -1085,7 +1085,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
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/* QEMU specific operations. */
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case INDEX_op_exit_tb:
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next_tb = *(uint64_t *)tb_ptr;
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ret = *(uint64_t *)tb_ptr;
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goto exit;
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break;
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case INDEX_op_goto_tb:
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@ -1243,5 +1243,5 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
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tci_assert(tb_ptr == old_code_ptr + op_size);
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}
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exit:
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return next_tb;
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return ret;
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}
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@ -1614,7 +1614,7 @@ kvm_failed_spr_get(int str, const char *msg) "Warning: Unable to retrieve SPR %d
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# cpu-exec.c
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disable exec_tb(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR
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disable exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR
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disable exec_tb_exit(void *next_tb, unsigned int flags) "tb:%p flags=%x"
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disable exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=%x"
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# translate-all.c
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translate_block(void *tb, uintptr_t pc, uint8_t *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p"
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