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cputlb: modernise the debug support
To avoid cluttering the code with #ifdef legs we wrap up the print statements into a tlb_debug() macro. As access to the virtual TLB can get quite heavy defining DEBUG_TLB_LOG will ensure all the logs go to the qemu_log target of CPU_LOG_MMU instead of stderr. This remains compile time optional as these debug statements haven't been considered for usefulness for user visible logging. I've also removed DEBUG_TLB_CHECK which wasn't used. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1458052224-9316-11-git-send-email-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Alex Bennée
Paolo Bonzini
parent
f6880b7f48
commit
8526e1f4e4
88
cputlb.c
88
cputlb.c
@ -30,8 +30,30 @@
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#include "exec/ram_addr.h"
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#include "tcg/tcg.h"
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//#define DEBUG_TLB
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//#define DEBUG_TLB_CHECK
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/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
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/* #define DEBUG_TLB */
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/* #define DEBUG_TLB_LOG */
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#ifdef DEBUG_TLB
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# define DEBUG_TLB_GATE 1
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# ifdef DEBUG_TLB_LOG
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# define DEBUG_TLB_LOG_GATE 1
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# else
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# define DEBUG_TLB_LOG_GATE 0
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# endif
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#else
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# define DEBUG_TLB_GATE 0
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# define DEBUG_TLB_LOG_GATE 0
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#endif
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#define tlb_debug(fmt, ...) do { \
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if (DEBUG_TLB_LOG_GATE) { \
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qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \
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## __VA_ARGS__); \
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} else if (DEBUG_TLB_GATE) { \
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fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
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} \
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} while (0)
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/* statistics */
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int tlb_flush_count;
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@ -52,9 +74,8 @@ void tlb_flush(CPUState *cpu, int flush_global)
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{
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CPUArchState *env = cpu->env_ptr;
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#if defined(DEBUG_TLB)
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printf("tlb_flush:\n");
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#endif
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tlb_debug("(%d)\n", flush_global);
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/* must reset current TB so that interrupts cannot modify the
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links while we are modifying them */
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cpu->current_tb = NULL;
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@ -73,9 +94,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
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{
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CPUArchState *env = cpu->env_ptr;
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#if defined(DEBUG_TLB)
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printf("tlb_flush_by_mmuidx:");
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#endif
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tlb_debug("start\n");
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/* must reset current TB so that interrupts cannot modify the
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links while we are modifying them */
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cpu->current_tb = NULL;
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@ -87,18 +106,12 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
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break;
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}
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#if defined(DEBUG_TLB)
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printf(" %d", mmu_idx);
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#endif
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tlb_debug("%d\n", mmu_idx);
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memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
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memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
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}
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#if defined(DEBUG_TLB)
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printf("\n");
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#endif
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memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
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}
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@ -128,16 +141,14 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
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int i;
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int mmu_idx;
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#if defined(DEBUG_TLB)
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printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
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#endif
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tlb_debug("page :" TARGET_FMT_lx "\n", addr);
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/* Check if we need to flush due to large pages. */
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if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
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#if defined(DEBUG_TLB)
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printf("tlb_flush_page: forced full flush ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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env->tlb_flush_addr, env->tlb_flush_mask);
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#endif
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tlb_debug("forcing full flush ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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env->tlb_flush_addr, env->tlb_flush_mask);
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tlb_flush(cpu, 1);
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return;
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}
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@ -170,16 +181,14 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
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va_start(argp, addr);
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#if defined(DEBUG_TLB)
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printf("tlb_flush_page_by_mmu_idx: " TARGET_FMT_lx, addr);
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#endif
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tlb_debug("addr "TARGET_FMT_lx"\n", addr);
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/* Check if we need to flush due to large pages. */
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if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
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#if defined(DEBUG_TLB)
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printf(" forced full flush ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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env->tlb_flush_addr, env->tlb_flush_mask);
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#endif
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tlb_debug("forced full flush ("
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TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
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env->tlb_flush_addr, env->tlb_flush_mask);
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v_tlb_flush_by_mmuidx(cpu, argp);
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va_end(argp);
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return;
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@ -198,9 +207,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
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break;
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}
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#if defined(DEBUG_TLB)
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printf(" %d", mmu_idx);
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#endif
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tlb_debug("idx %d\n", mmu_idx);
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tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
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@ -211,10 +218,6 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
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}
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va_end(argp);
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#if defined(DEBUG_TLB)
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printf("\n");
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#endif
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tb_flush_jmp_cache(cpu, addr);
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}
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@ -367,12 +370,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
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assert(sz >= TARGET_PAGE_SIZE);
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#if defined(DEBUG_TLB)
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qemu_log_mask(CPU_LOG_MMU,
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"tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
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" prot=%x idx=%d\n",
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vaddr, paddr, prot, mmu_idx);
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#endif
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tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
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" prot=%x idx=%d\n",
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vaddr, paddr, prot, mmu_idx);
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address = vaddr;
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if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
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