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target/xtensa: extract debug helpers
Move HELPER functions related to native debugging from op_helper.c to dbg_helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
7e5e5a6302
commit
8803bfea0e
@ -7,6 +7,7 @@ obj-y += core-test_kc705_be.o
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obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o
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obj-y += xtensa-isa.o
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obj-y += translate.o op_helper.o helper.o cpu.o
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obj-$(CONFIG_SOFTMMU) += dbg_helper.o
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obj-y += fpu_helper.o
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obj-y += gdbstub.o
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obj-$(CONFIG_SOFTMMU) += mmu_helper.o
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129
target/xtensa/dbg_helper.c
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129
target/xtensa/dbg_helper.c
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@ -0,0 +1,129 @@
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/*
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* Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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#include "exec/address-spaces.h"
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static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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{
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
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&paddr, &page_size, &access);
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if (ret == 0) {
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tb_invalidate_phys_addr(&address_space_memory, paddr,
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MEMTXATTRS_UNSPECIFIED);
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}
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}
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void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
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{
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uint32_t change = v ^ env->sregs[IBREAKENABLE];
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unsigned i;
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for (i = 0; i < env->config->nibreak; ++i) {
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if (change & (1 << i)) {
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tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
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}
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}
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env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
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}
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void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
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tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
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tb_invalidate_virtual_addr(env, v);
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}
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env->sregs[IBREAKA + i] = v;
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}
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static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
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uint32_t dbreakc)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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uint32_t mask = dbreakc | ~DBREAKC_MASK;
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if (env->cpu_watchpoint[i]) {
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
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}
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if (dbreakc & DBREAKC_SB) {
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flags |= BP_MEM_WRITE;
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}
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if (dbreakc & DBREAKC_LB) {
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flags |= BP_MEM_READ;
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}
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/* contiguous mask after inversion is one less than some power of 2 */
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if ((~mask + 1) & ~mask) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
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/* cut mask after the first zero bit */
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mask = 0xffffffff << (32 - clo32(mask));
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}
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if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
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flags, &env->cpu_watchpoint[i])) {
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env->cpu_watchpoint[i] = NULL;
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qemu_log_mask(LOG_GUEST_ERROR,
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"Failed to set data breakpoint at 0x%08x/%d\n",
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dbreaka & mask, ~mask + 1);
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}
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}
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void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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uint32_t dbreakc = env->sregs[DBREAKC + i];
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if ((dbreakc & DBREAKC_SB_LB) &&
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env->sregs[DBREAKA + i] != v) {
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set_dbreak(env, i, v, dbreakc);
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}
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env->sregs[DBREAKA + i] = v;
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}
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void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
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if (v & DBREAKC_SB_LB) {
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set_dbreak(env, i, env->sregs[DBREAKA + i], v);
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} else {
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if (env->cpu_watchpoint[i]) {
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
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env->cpu_watchpoint[i] = NULL;
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}
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}
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}
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env->sregs[DBREAKC + i] = v;
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}
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@ -93,19 +93,6 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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addr);
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}
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static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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{
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
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&paddr, &page_size, &access);
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if (ret == 0) {
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tb_invalidate_phys_addr(&address_space_memory, paddr,
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MEMTXATTRS_UNSPECIFIED);
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}
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}
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#endif
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void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
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@ -325,85 +312,6 @@ void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v)
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env->sregs[MEMCTL] = v & env->config->memctl_mask;
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}
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void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
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{
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uint32_t change = v ^ env->sregs[IBREAKENABLE];
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unsigned i;
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for (i = 0; i < env->config->nibreak; ++i) {
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if (change & (1 << i)) {
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tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
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}
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}
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env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
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}
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void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
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tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
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tb_invalidate_virtual_addr(env, v);
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}
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env->sregs[IBREAKA + i] = v;
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}
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static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
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uint32_t dbreakc)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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uint32_t mask = dbreakc | ~DBREAKC_MASK;
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if (env->cpu_watchpoint[i]) {
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
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}
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if (dbreakc & DBREAKC_SB) {
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flags |= BP_MEM_WRITE;
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}
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if (dbreakc & DBREAKC_LB) {
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flags |= BP_MEM_READ;
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}
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/* contiguous mask after inversion is one less than some power of 2 */
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if ((~mask + 1) & ~mask) {
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qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
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/* cut mask after the first zero bit */
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mask = 0xffffffff << (32 - clo32(mask));
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}
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if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
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flags, &env->cpu_watchpoint[i])) {
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env->cpu_watchpoint[i] = NULL;
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qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n",
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dbreaka & mask, ~mask + 1);
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}
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}
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void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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uint32_t dbreakc = env->sregs[DBREAKC + i];
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if ((dbreakc & DBREAKC_SB_LB) &&
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env->sregs[DBREAKA + i] != v) {
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set_dbreak(env, i, v, dbreakc);
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}
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env->sregs[DBREAKA + i] = v;
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}
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void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
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{
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if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
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if (v & DBREAKC_SB_LB) {
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set_dbreak(env, i, env->sregs[DBREAKA + i], v);
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} else {
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if (env->cpu_watchpoint[i]) {
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
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env->cpu_watchpoint[i] = NULL;
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}
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}
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}
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env->sregs[DBREAKC + i] = v;
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}
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#endif
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uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr)
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