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hw/arm/armsse: Add SSE-300 support

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Now we have sufficiently parameterised the code, we can add SSE-300
support by adding a new entry to the armsse_variants[] array.

Note that the main watchdog (unlike the s32k watchdog) in the SSE-300
is a different device from the CMSDK watchdog; we don't have a model
of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-36-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:46:08 +00:00
parent 4668b441cb
commit 8901bb414a
2 changed files with 153 additions and 0 deletions
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152
hw/arm/armsse.c
View File

@ -337,6 +337,128 @@ static const ARMSSEDeviceInfo sse200_devices[] = {
}
};
static const ARMSSEDeviceInfo sse300_devices[] = {
{
.name = "timer0",
.type = TYPE_SSE_TIMER,
.index = 0,
.addr = 0x48000000,
.ppc = 0,
.ppc_port = 0,
.irq = 3,
},
{
.name = "timer1",
.type = TYPE_SSE_TIMER,
.index = 1,
.addr = 0x48001000,
.ppc = 0,
.ppc_port = 1,
.irq = 4,
},
{
.name = "timer2",
.type = TYPE_SSE_TIMER,
.index = 2,
.addr = 0x48002000,
.ppc = 0,
.ppc_port = 2,
.irq = 5,
},
{
.name = "timer3",
.type = TYPE_SSE_TIMER,
.index = 3,
.addr = 0x48003000,
.ppc = 0,
.ppc_port = 5,
.irq = 27,
},
{
.name = "s32ktimer",
.type = TYPE_CMSDK_APB_TIMER,
.index = 0,
.addr = 0x4802f000,
.ppc = 1,
.ppc_port = 0,
.irq = 2,
.slowclk = true,
},
{
.name = "s32kwatchdog",
.type = TYPE_CMSDK_APB_WATCHDOG,
.index = 0,
.addr = 0x4802e000,
.ppc = NO_PPC,
.irq = NMI_0,
.slowclk = true,
},
{
.name = "watchdog",
.type = TYPE_UNIMPLEMENTED_DEVICE,
.index = 0,
.addr = 0x48040000,
.size = 0x2000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "armsse-sysinfo",
.type = TYPE_IOTKIT_SYSINFO,
.index = 0,
.addr = 0x48020000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "armsse-sysctl",
.type = TYPE_IOTKIT_SYSCTL,
.index = 0,
.addr = 0x58021000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "SYS_PPU",
.type = TYPE_UNIMPLEMENTED_DEVICE,
.index = 1,
.addr = 0x58022000,
.size = 0x1000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "CPU0CORE_PPU",
.type = TYPE_UNIMPLEMENTED_DEVICE,
.index = 2,
.addr = 0x50023000,
.size = 0x1000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "MGMT_PPU",
.type = TYPE_UNIMPLEMENTED_DEVICE,
.index = 3,
.addr = 0x50028000,
.size = 0x1000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = "DEBUG_PPU",
.type = TYPE_UNIMPLEMENTED_DEVICE,
.index = 4,
.addr = 0x50029000,
.size = 0x1000,
.ppc = NO_PPC,
.irq = NO_IRQ,
},
{
.name = NULL,
}
};
/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
static const bool sse200_irq_is_common[32] = {
[0 ... 5] = true,
@ -352,6 +474,18 @@ static const bool sse200_irq_is_common[32] = {
/* 30, 31: reserved */
};
static const bool sse300_irq_is_common[32] = {
[0 ... 5] = true,
/* 6, 7: per-CPU MHU interrupts */
[8 ... 12] = true,
/* 13: reserved */
[14 ... 16] = true,
/* 17-25: reserved */
[26 ... 27] = true,
/* 28, 29: per-CPU CTI interrupts */
/* 30, 31: reserved */
};
static const ARMSSEInfo armsse_variants[] = {
{
.name = TYPE_IOTKIT,
@ -389,6 +523,24 @@ static const ARMSSEInfo armsse_variants[] = {
.devinfo = sse200_devices,
.irq_is_common = sse200_irq_is_common,
},
{
.name = TYPE_SSE300,
.sse_version = ARMSSE_SSE300,
.sram_banks = 2,
.num_cpus = 1,
.sys_version = 0x7e00043b,
.iidr = 0x74a0043b,
.cpuwait_rst = 0,
.has_mhus = false,
.has_cachectrl = false,
.has_cpusecctrl = true,
.has_cpuid = true,
.has_cpu_pwrctrl = true,
.has_sse_counter = true,
.props = armsse_properties,
.devinfo = sse300_devices,
.irq_is_common = sse300_irq_is_common,
},
};
static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)

1
include/hw/arm/armsse.h
View File

@ -123,6 +123,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
*/
#define TYPE_IOTKIT "iotkit"
#define TYPE_SSE200 "sse-200"
#define TYPE_SSE300 "sse-300"
/* We have an IRQ splitter and an OR gate input for each external PPC
* and the 2 internal PPCs