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target/riscv: Add hfence instructions

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:02:36 -08:00 committed by Palmer Dabbelt
parent e3fba4bab6
commit 895c412cb6
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GPG Key ID: 2E1319F35FBB1889
2 changed files with 54 additions and 9 deletions
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23
target/riscv/insn32.decode
View File

@ -63,20 +63,25 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
# *** Privileged Instructions *** # *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011 ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011
hret 0010000 00010 00000 000 00000 1110011 hret 0010000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
# *** RV32I Base Instruction Set *** # *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u lui .................... ..... 0110111 @u

40
target/riscv/insn_trans/trans_privileged.inc.c
View File

@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
#endif #endif
return false; return false;
} }
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(cpu_env);
return true;
/* } */
}
#endif
return false;
}
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
* (env->priv == PRV_S &&
* !riscv_cpu_virt_enabled(env) &&
* get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
*/
gen_helper_tlb_flush(cpu_env);
return true;
/* } */
}
#endif
return false;
}