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Merge remote-tracking branch 'afaerber/qom-cpu' into staging

Browse Source 
# By Andreas Färber
# Via Andreas Färber
* afaerber/qom-cpu:
  linux-user: bsd-user: Don't reset X86CPU twice
  target-i386: Pass X86CPU to cpu_x86_set_a20()
  target-unicore32: Rename CPU subtypes
  target-openrisc: Rename CPU subtypes
  target-openrisc: TYPE_OPENRISC_CPU should be abstract
  target-m68k: Rename CPU subtypes
  target-m68k: Mark as unmigratable
  target-s390x: Mark as unmigratable
  target-sh4: Mark as unmigratable
  target-xtensa: Mark as unmigratable
  target-microblaze: Mark as unmigratable
  target-unicore32: Mark as unmigratable
  ide/mmio: QOM'ify MMIO IDE for R2D
This commit is contained in:
Anthony Liguori 2013-01-31 19:37:33 -06:00
commit 8a55ebf015
31 changed files with 180 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bsd-user/main.c
View File

@ -917,7 +917,7 @@ int main(int argc, char **argv)
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(ENV_GET_CPU(env));
#endif
thread_env = env;

5
hw/ide.h
View File

@ -20,10 +20,7 @@ PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
/* ide-mmio.c */
void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1);
int ide_get_geometry(BusState *bus, int unit,
int16_t *cyls, int8_t *heads, int8_t *secs);

92
hw/ide/mmio.c
View File

@ -22,7 +22,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <hw/hw.h>
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "block/block.h"
#include "sysemu/dma.h"
@ -34,15 +35,24 @@
* dedicated ide controller, which is often seen on embedded boards.
*/
typedef struct {
#define TYPE_MMIO_IDE "mmio-ide"
#define MMIO_IDE(obj) OBJECT_CHECK(MMIOState, (obj), TYPE_MMIO_IDE)
typedef struct MMIOIDEState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
IDEBus bus;
int shift;
uint32_t shift;
qemu_irq irq;
MemoryRegion iomem1, iomem2;
} MMIOState;
static void mmio_ide_reset(void *opaque)
static void mmio_ide_reset(DeviceState *dev)
{
MMIOState *s = opaque;
MMIOState *s = MMIO_IDE(dev);
ide_bus_reset(&s->bus);
}
@ -107,24 +117,68 @@ static const VMStateDescription vmstate_ide_mmio = {
}
};
void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
{
MMIOState *s = g_malloc0(sizeof(MMIOState));
SysBusDevice *d = SYS_BUS_DEVICE(dev);
MMIOState *s = MMIO_IDE(dev);
ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);
s->shift = shift;
ide_init2(&s->bus, s->irq);
memory_region_init_io(&s->iomem1, &mmio_ide_ops, s,
"ide-mmio.1", 16 << shift);
"ide-mmio.1", 16 << s->shift);
memory_region_init_io(&s->iomem2, &mmio_ide_cs_ops, s,
"ide-mmio.2", 2 << shift);
memory_region_add_subregion(address_space, membase, &s->iomem1);
memory_region_add_subregion(address_space, membase2, &s->iomem2);
vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
qemu_register_reset(mmio_ide_reset, s);
"ide-mmio.2", 2 << s->shift);
sysbus_init_mmio(d, &s->iomem1);
sysbus_init_mmio(d, &s->iomem2);
}
static void mmio_ide_initfn(Object *obj)
{
SysBusDevice *d = SYS_BUS_DEVICE(obj);
MMIOState *s = MMIO_IDE(obj);
ide_bus_new(&s->bus, DEVICE(obj), 0);
sysbus_init_irq(d, &s->irq);
}
static Property mmio_ide_properties[] = {
DEFINE_PROP_UINT32("shift", MMIOState, shift, 0),
DEFINE_PROP_END_OF_LIST()
};
static void mmio_ide_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = mmio_ide_realizefn;
dc->reset = mmio_ide_reset;
dc->props = mmio_ide_properties;
dc->vmsd = &vmstate_ide_mmio;
}
static const TypeInfo mmio_ide_type_info = {
.name = TYPE_MMIO_IDE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MMIOState),
.instance_init = mmio_ide_initfn,
.class_init = mmio_ide_class_init,
};
static void mmio_ide_register_types(void)
{
type_register_static(&mmio_ide_type_info);
}
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1)
{
MMIOState *s = MMIO_IDE(dev);
if (hd0 != NULL) {
ide_create_drive(&s->bus, 0, hd0);
}
if (hd1 != NULL) {
ide_create_drive(&s->bus, 1, hd1);
}
}
type_init(mmio_ide_register_types)

7
hw/pc.c
View File

@ -527,11 +527,11 @@ type_init(port92_register_types)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
CPUX86State *cpu = opaque;
X86CPU *cpu = opaque;
/* XXX: send to all CPUs ? */
/* XXX: add logic to handle multiple A20 line sources */
cpu_x86_set_a20(cpu, level);
x86_cpu_set_a20(cpu, level);
}
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
@ -1085,7 +1085,8 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
}
}
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
a20_line = qemu_allocate_irqs(handle_a20_line_change,
x86_env_get_cpu(first_cpu), 2);
i8042 = isa_create_simple(isa_bus, "i8042");
i8042_setup_a20_line(i8042, &a20_line[0]);
if (!no_vmport) {

10
hw/r2d.c
View File

@ -276,8 +276,14 @@ static void r2d_init(QEMUMachineInitArgs *args)
/* onboard CF (True IDE mode, Master only). */
dinfo = drive_get(IF_IDE, 0, 0);
mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1,
dinfo, NULL);
dev = qdev_create(NULL, "mmio-ide");
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
qdev_prop_set_uint32(dev, "shift", 1);
qdev_init_nofail(dev);
sysbus_mmio_map(busdev, 0, 0x14001000);
sysbus_mmio_map(busdev, 1, 0x1400080c);
mmio_ide_init_drives(dev, dinfo, NULL);
/* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0);

2
linux-user/main.c
View File

@ -3540,7 +3540,7 @@ int main(int argc, char **argv, char **envp)
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(ENV_GET_CPU(env));
#endif

2
target-i386/cpu.h
View File

@ -1011,7 +1011,7 @@ void host_cpuid(uint32_t function, uint32_t count,
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write, int mmu_idx);
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
{

4
target-i386/helper.c
View File

@ -366,8 +366,10 @@ void cpu_dump_state(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
/* x86 mmu */
/* XXX: add PGE support */
void cpu_x86_set_a20(CPUX86State *env, int a20_state)
void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
{
CPUX86State *env = &cpu->env;
a20_state = (a20_state != 0);
if (a20_state != ((env->a20_mask >> 20) & 1)) {
#if defined(DEBUG_MMU)

1
target-m68k/Makefile.objs
View File

@ -1,3 +1,2 @@
obj-y += m68k-semi.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o

16
target-m68k/cpu.c
View File

@ -20,6 +20,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "migration/vmstate.h"
static void m68k_set_feature(CPUM68KState *env, int feature)
@ -58,12 +59,15 @@ static void m68k_cpu_reset(CPUState *s)
static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename;
if (cpu_model == NULL) {
return NULL;
}
oc = object_class_by_name(cpu_model);
typename = g_strdup_printf("%s-" TYPE_M68K_CPU, cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL ||
object_class_is_abstract(oc))) {
return NULL;
@ -143,26 +147,34 @@ static void m68k_cpu_initfn(Object *obj)
cpu_exec_init(env);
}
static const VMStateDescription vmstate_m68k_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void m68k_cpu_class_init(ObjectClass *c, void *data)
{
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
mcc->parent_reset = cc->reset;
cc->reset = m68k_cpu_reset;
cc->class_by_name = m68k_cpu_class_by_name;
dc->vmsd = &vmstate_m68k_cpu;
}
static void register_cpu_type(const M68kCPUInfo *info)
{
TypeInfo type_info = {
.name = info->name,
.parent = TYPE_M68K_CPU,
.instance_init = info->instance_init,
};
type_info.name = g_strdup_printf("%s-" TYPE_M68K_CPU, info->name);
type_register(&type_info);
g_free((void *)type_info.name);
}
static const TypeInfo m68k_cpu_type_info = {

11
target-m68k/helper.c
View File

@ -34,9 +34,9 @@ static gint m68k_cpu_list_compare(gconstpointer a, gconstpointer b)
name_a = object_class_get_name(class_a);
name_b = object_class_get_name(class_b);
if (strcmp(name_a, "any") == 0) {
if (strcmp(name_a, "any-" TYPE_M68K_CPU) == 0) {
return 1;
} else if (strcmp(name_b, "any") == 0) {
} else if (strcmp(name_b, "any-" TYPE_M68K_CPU) == 0) {
return -1;
} else {
return strcasecmp(name_a, name_b);
@ -47,9 +47,14 @@ static void m68k_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *c = data;
CPUListState *s = user_data;
const char *typename;
char *name;
typename = object_class_get_name(c);
name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_M68K_CPU));
(*s->cpu_fprintf)(s->file, "%s\n",
object_class_get_name(c));
name);
g_free(name);
}
void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)

0
target-m68k/machine.c
View File

2
target-microblaze/Makefile.objs
View File

@ -1,2 +1,2 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
obj-$(CONFIG_SOFTMMU) += mmu.o

9
target-microblaze/cpu.c
View File

@ -22,6 +22,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "migration/vmstate.h"
/* CPUClass::reset() */
@ -94,13 +95,21 @@ static void mb_cpu_initfn(Object *obj)
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
}
static const VMStateDescription vmstate_mb_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
dc->vmsd = &vmstate_mb_cpu;
}
static const TypeInfo mb_cpu_type_info = {

2
target-microblaze/cpu.h
View File

@ -307,8 +307,6 @@ static inline CPUMBState *cpu_init(const char *cpu_model)
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler
#define CPU_SAVE_VERSION 1
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel

11
target-microblaze/machine.c
View File

@ -1,11 +0,0 @@
#include "hw/hw.h"
#include "hw/boards.h"
void cpu_save(QEMUFile *f, void *opaque)
{
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
return 0;
}

17
target-openrisc/cpu.c
View File

@ -144,14 +144,15 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
static void cpu_register(const OpenRISCCPUInfo *info)
{
TypeInfo type_info = {
.name = info->name,
.parent = TYPE_OPENRISC_CPU,
.instance_size = sizeof(OpenRISCCPU),
.instance_init = info->initfn,
.class_size = sizeof(OpenRISCCPUClass),
};
type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
type_register(&type_info);
g_free((void *)type_info.name);
}
static const TypeInfo openrisc_cpu_type_info = {
@ -159,7 +160,7 @@ static const TypeInfo openrisc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(OpenRISCCPU),
.instance_init = openrisc_cpu_initfn,
.abstract = false,
.abstract = true,
.class_size = sizeof(OpenRISCCPUClass),
.class_init = openrisc_cpu_class_init,
};
@ -200,9 +201,9 @@ static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
name_a = object_class_get_name(class_a);
name_b = object_class_get_name(class_b);
if (strcmp(name_a, "any") == 0) {
if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
return 1;
} else if (strcmp(name_b, "any") == 0) {
} else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
return -1;
} else {
return strcmp(name_a, name_b);
@ -213,9 +214,15 @@ static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
CPUListState *s = user_data;
const char *typename;
char *name;
typename = object_class_get_name(oc);
name = g_strndup(typename,
strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
(*s->cpu_fprintf)(s->file, " %s\n",
object_class_get_name(oc));
name);
g_free(name);
}
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)

2
target-s390x/Makefile.objs
View File

@ -1,4 +1,4 @@
obj-y += translate.o helper.o cpu.o interrupt.o
obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o
obj-$(CONFIG_SOFTMMU) += ioinst.o
obj-$(CONFIG_KVM) += kvm.o

10
target-s390x/cpu.c
View File

@ -26,8 +26,8 @@
#include "cpu.h"
#include "qemu-common.h"
#include "qemu/timer.h"
#ifndef CONFIG_USER_ONLY
#include "hw/hw.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/arch_init.h"
#endif
@ -135,13 +135,21 @@ static void s390_cpu_finalize(Object *obj)
#endif
}
static const VMStateDescription vmstate_s390_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void s390_cpu_class_init(ObjectClass *oc, void *data)
{
S390CPUClass *scc = S390_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(scc);
DeviceClass *dc = DEVICE_CLASS(oc);
scc->parent_reset = cc->reset;
cc->reset = s390_cpu_reset;
dc->vmsd = &vmstate_s390_cpu;
}
static const TypeInfo s390_cpu_type_info = {

30
target-s390x/machine.c
View File

@ -1,30 +0,0 @@
/*
* QEMU S390x machine definitions
*
* Copyright (c) 2009 Alexander Graf <agraf@suse.de>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw/hw.h"
#include "hw/boards.h"
void cpu_save(QEMUFile *f, void *opaque)
{
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
return 0;
}

1
target-sh4/Makefile.objs
View File

@ -1,2 +1 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o

9
target-sh4/cpu.c
View File

@ -21,6 +21,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "migration/vmstate.h"
/* CPUClass::reset() */
@ -63,13 +64,21 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void superh_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->parent_reset = cc->reset;
cc->reset = superh_cpu_reset;
dc->vmsd = &vmstate_sh_cpu;
}
static const TypeInfo superh_cpu_type_info = {

0
target-sh4/machine.c
View File

2
target-unicore32/Makefile.objs
View File

@ -1,4 +1,4 @@
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += ucf64_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
obj-$(CONFIG_SOFTMMU) += softmmu.o

17
target-unicore32/cpu.c
View File

@ -14,6 +14,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "migration/vmstate.h"
static inline void set_feature(CPUUniCore32State *env, int feature)
{
@ -25,12 +26,15 @@ static inline void set_feature(CPUUniCore32State *env, int feature)
static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
char *typename;
if (cpu_model == NULL) {
return NULL;
}
oc = object_class_by_name(cpu_model);
typename = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, cpu_model);
oc = object_class_by_name(typename);
g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) ||
object_class_is_abstract(oc))) {
oc = NULL;
@ -83,7 +87,6 @@ static void uc32_cpu_initfn(Object *obj)
CPUUniCore32State *env = &cpu->env;
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
@ -96,22 +99,30 @@ static void uc32_cpu_initfn(Object *obj)
tlb_flush(env, 1);
}
static const VMStateDescription vmstate_uc32_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void uc32_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
cc->class_by_name = uc32_cpu_class_by_name;
dc->vmsd = &vmstate_uc32_cpu;
}
static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
{
TypeInfo type_info = {
.name = info->name,
.parent = TYPE_UNICORE32_CPU,
.instance_init = info->instance_init,
};
type_info.name = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, info->name);
type_register(&type_info);
g_free((void *)type_info.name);
}
static const TypeInfo uc32_cpu_type_info = {

2
target-unicore32/cpu.h
View File

@ -133,8 +133,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
int mmu_idx);
#define CPU_SAVE_VERSION 2
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user

1
target-unicore32/helper.c
View File

@ -38,6 +38,7 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
}
cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
env->cpu_model_str = cpu_model;
if (inited) {
inited = 0;

23
target-unicore32/machine.c
View File

@ -1,23 +0,0 @@
/*
* Generic machine functions for UniCore32 ISA
*
* Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation, or any later version.
* See the COPYING file in the top-level directory.
*/
#include "hw/hw.h"
void cpu_save(QEMUFile *f, void *opaque)
{
hw_error("%s not supported yet.\n", __func__);
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
hw_error("%s not supported yet.\n", __func__);
return 0;
}

1
target-xtensa/Makefile.objs
View File

@ -3,4 +3,3 @@ obj-y += core-dc232b.o
obj-y += core-dc233c.o
obj-y += core-fsf.o
obj-y += translate.o op_helper.o helper.o cpu.o
obj-$(CONFIG_SOFTMMU) += machine.o

9
target-xtensa/cpu.c
View File

@ -30,6 +30,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "migration/vmstate.h"
/* CPUClass::reset() */
@ -64,13 +65,21 @@ static void xtensa_cpu_initfn(Object *obj)
cpu_exec_init(env);
}
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
xcc->parent_reset = cc->reset;
cc->reset = xtensa_cpu_reset;
dc->vmsd = &vmstate_xtensa_cpu;
}
static const TypeInfo xtensa_cpu_type_info = {

38
target-xtensa/machine.c
View File

@ -1,38 +0,0 @@
/*
* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "hw/hw.h"
#include "hw/boards.h"
void cpu_save(QEMUFile *f, void *opaque)
{
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
return 0;
}