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tcg-ppc64: Fix RLDCL opcode

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The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.

Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories.

Cc: qemu-stable@nongnu.org
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Anton Blanchard 2013-06-11 21:19:35 +10:00 committed by Richard Henderson
parent 38aea177d9
commit 8a94cfb05e
1 changed files with 6 additions and 5 deletions
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11
tcg/ppc64/tcg-target.c
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@ -308,7 +308,8 @@ static int tcg_target_const_match (tcg_target_long val,
#define OPCD(opc) ((opc)<<26)
#define XO19(opc) (OPCD(19)|((opc)<<1))
#define XO30(opc) (OPCD(30)|((opc)<<2))
#define MD30(opc) (OPCD(30)|((opc)<<2))
#define MDS30(opc) (OPCD(30)|((opc)<<1))
#define XO31(opc) (OPCD(31)|((opc)<<1))
#define XO58(opc) (OPCD(58)|(opc))
#define XO62(opc) (OPCD(62)|(opc))
@ -354,10 +355,10 @@ static int tcg_target_const_match (tcg_target_long val,
#define RLWINM OPCD( 21)
#define RLWNM OPCD( 23)
#define RLDICL XO30( 0)
#define RLDICR XO30( 1)
#define RLDIMI XO30( 3)
#define RLDCL XO30( 8)
#define RLDICL MD30( 0)
#define RLDICR MD30( 1)
#define RLDIMI MD30( 3)
#define RLDCL MDS30( 8)
#define BCLR XO19( 16)
#define BCCTR XO19(528)