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target-microblaze: Preserve the pvr registers during reset
Move the Microblaze PVR registers to the end of the CPUMBState and preserve them during reset. This is similar to what the QEMU ARM model does with some of it's registers. This allows the Microblaze PVR registers to only be set once at realise instead of constantly at reset. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -63,13 +63,34 @@ static void mb_cpu_reset(CPUState *s)
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mcc->parent_reset(s);
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memset(env, 0, sizeof(CPUMBState));
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memset(env, 0, offsetof(CPUMBState, pvr));
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env->res_addr = RES_ADDR_NONE;
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tlb_flush(s, 1);
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/* Disable stack protector. */
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env->shr = ~0;
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
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#else
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env->sregs[SR_MSR] = 0;
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mmu_init(&env->mmu);
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env->mmu.c_mmu = 3;
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env->mmu.c_mmu_tlb_access = 3;
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env->mmu.c_mmu_zones = 16;
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#endif
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}
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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qemu_init_vcpu(cs);
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env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
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| PVR0_USE_BARREL_MASK \
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| PVR0_USE_DIV_MASK \
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@ -99,25 +120,8 @@ static void mb_cpu_reset(CPUState *s)
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env->sregs[SR_PC] = cpu->base_vectors;
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#if defined(CONFIG_USER_ONLY)
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/* start in user mode with interrupts enabled. */
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env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
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env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
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#else
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env->sregs[SR_MSR] = 0;
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mmu_init(&env->mmu);
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env->mmu.c_mmu = 3;
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env->mmu.c_mmu_tlb_access = 3;
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env->mmu.c_mmu_zones = 16;
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#endif
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}
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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mcc->parent_realize(dev, errp);
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}
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@ -260,16 +260,18 @@ struct CPUMBState {
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#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
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uint32_t iflags;
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struct {
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uint32_t regs[16];
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} pvr;
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#if !defined(CONFIG_USER_ONLY)
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/* Unified MMU. */
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struct microblaze_mmu mmu;
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#endif
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CPU_COMMON
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/* These fields are preserved on reset. */
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struct {
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uint32_t regs[16];
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} pvr;
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};
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#include "cpu-qom.h"
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