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spapr: Remove SpaprIrq::nr_msis
The nr_msis value we use here has to line up with whether we're using legacy or modern irq allocation. Therefore it's safer to derive it based on legacy_irq_allocation rather than having SpaprIrq contain a canned value. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
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605994e5b7
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8cbe71ecb8
@ -1267,7 +1267,7 @@ static void *spapr_build_fdt(SpaprMachineState *spapr)
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}
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QLIST_FOREACH(phb, &spapr->phbs, list) {
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ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL);
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ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
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if (ret < 0) {
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error_report("couldn't setup PCI devices in fdt");
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exit(1);
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@ -3905,8 +3905,7 @@ int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
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return -1;
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}
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if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis,
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fdt_start_offset)) {
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if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
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error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
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return -1;
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}
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@ -29,9 +29,14 @@ static const TypeInfo spapr_intc_info = {
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.class_size = sizeof(SpaprInterruptControllerClass),
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};
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis)
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static void spapr_irq_msi_init(SpaprMachineState *spapr)
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{
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spapr->irq_map_nr = nr_msis;
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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/* Legacy mode doesn't use this allocator */
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return;
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}
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spapr->irq_map_nr = spapr_irq_nr_msis(spapr);
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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@ -102,7 +107,6 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
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SpaprIrq spapr_irq_xics = {
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.nr_xirqs = SPAPR_NR_XIRQS,
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.nr_msis = SPAPR_NR_MSIS,
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.xics = true,
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.xive = false,
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};
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@ -113,7 +117,6 @@ SpaprIrq spapr_irq_xics = {
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SpaprIrq spapr_irq_xive = {
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.nr_xirqs = SPAPR_NR_XIRQS,
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.nr_msis = SPAPR_NR_MSIS,
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.xics = false,
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.xive = true,
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};
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@ -132,7 +135,6 @@ SpaprIrq spapr_irq_xive = {
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*/
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SpaprIrq spapr_irq_dual = {
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.nr_xirqs = SPAPR_NR_XIRQS,
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.nr_msis = SPAPR_NR_MSIS,
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.xics = true,
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.xive = true,
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};
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@ -247,6 +249,15 @@ void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
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sicc->dt(spapr->active_intc, nr_servers, fdt, phandle);
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}
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uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr)
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{
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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return spapr->irq->nr_xirqs;
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} else {
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return SPAPR_XIRQ_BASE + spapr->irq->nr_xirqs - SPAPR_IRQ_MSI;
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}
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}
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
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{
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MachineState *machine = MACHINE(spapr);
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@ -267,9 +278,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
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}
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/* Initialize the MSI IRQ allocator. */
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
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}
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spapr_irq_msi_init(spapr);
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if (spapr->irq->xics) {
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Error *local_err = NULL;
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@ -551,7 +560,6 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
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SpaprIrq spapr_irq_xics_legacy = {
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.nr_xirqs = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS,
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.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS,
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.xics = true,
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.xive = false,
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};
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@ -2277,8 +2277,8 @@ static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
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}
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int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
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uint32_t nr_msis, int *node_offset)
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int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
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uint32_t intc_phandle, void *fdt, int *node_offset)
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{
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int bus_off, i, j, ret;
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uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
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@ -2343,7 +2343,8 @@ int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
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_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
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_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis));
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
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spapr_irq_nr_msis(spapr)));
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/* Dynamic DMA window */
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if (phb->ddw_enabled) {
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@ -128,8 +128,8 @@ struct SpaprPhbState {
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#define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
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64 * KiB)
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int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
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uint32_t nr_msis, int *node_offset);
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int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
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uint32_t intc_phandle, void *fdt, int *node_offset);
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void spapr_pci_rtas_init(void);
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@ -27,7 +27,6 @@
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#define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
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#define SPAPR_NR_XIRQS 0x1000
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#define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
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typedef struct SpaprMachineState SpaprMachineState;
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@ -73,14 +72,13 @@ void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
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void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle);
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
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uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr);
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp);
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
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typedef struct SpaprIrq {
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uint32_t nr_xirqs;
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uint32_t nr_msis;
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bool xics;
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bool xive;
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} SpaprIrq;
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