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qtest/ahci: finalize AHCIQState consolidation
Move barsize, ahci_fingerprint and capabilities registers into the AHCIQState object, removing global ahci-related state from the ahci-test.c file. More churn, less globals. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1421698563-6977-10-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
John Snow
Stefan Hajnoczi
parent
6100ddb0f9
commit
8d5eeceddc
@ -46,10 +46,8 @@
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/*** Globals ***/
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static QGuestAllocator *guest_malloc;
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static QPCIBus *pcibus;
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static uint64_t barsize;
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static char tmp_path[] = "/tmp/qtest.XXXXXX";
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static bool ahci_pedantic;
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static uint32_t ahci_fingerprint;
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/*** IO macros for the AHCI memory registers. ***/
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#define AHCI_READ(OFST) qpci_io_readl(ahci->dev, ahci->hba_base + (OFST))
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@ -70,12 +68,11 @@ static uint32_t ahci_fingerprint;
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PX_RREG((port), (reg)) & ~(mask));
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/*** Function Declarations ***/
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static QPCIDevice *get_ahci_device(void);
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static QPCIDevice *get_ahci_device(uint32_t *fingerprint);
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static void start_ahci_device(AHCIQState *ahci);
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static void free_ahci_device(QPCIDevice *dev);
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static void ahci_test_port_spec(AHCIQState *ahci,
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HBACap *hcap, uint8_t port);
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static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
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static void ahci_test_pci_spec(AHCIQState *ahci);
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static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
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uint8_t offset);
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@ -99,9 +96,10 @@ static void string_bswap16(uint16_t *s, size_t bytes)
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/**
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* Locate, verify, and return a handle to the AHCI device.
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*/
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static QPCIDevice *get_ahci_device(void)
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static QPCIDevice *get_ahci_device(uint32_t *fingerprint)
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{
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QPCIDevice *ahci;
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uint32_t ahci_fingerprint;
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pcibus = qpci_init_pc();
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@ -119,6 +117,9 @@ static QPCIDevice *get_ahci_device(void)
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g_assert_not_reached();
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}
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if (fingerprint) {
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*fingerprint = ahci_fingerprint;
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}
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return ahci;
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}
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@ -131,9 +132,6 @@ static void free_ahci_device(QPCIDevice *ahci)
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qpci_free_pc(pcibus);
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pcibus = NULL;
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}
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/* Clear our cached barsize information. */
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barsize = 0;
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}
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/*** Test Setup & Teardown ***/
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@ -156,7 +154,7 @@ static AHCIQState *ahci_boot(void)
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s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
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/* Verify that we have an AHCI device present. */
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s->dev = get_ahci_device();
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s->dev = get_ahci_device(&s->fingerprint);
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/* Stopgap: Copy the allocator reference */
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guest_malloc = s->parent->alloc;
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@ -186,7 +184,7 @@ static void ahci_pci_enable(AHCIQState *ahci)
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start_ahci_device(ahci);
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switch (ahci_fingerprint) {
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switch (ahci->fingerprint) {
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case AHCI_INTEL_ICH9:
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/* ICH9 has a register at PCI 0x92 that
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* acts as a master port enabler mask. */
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@ -206,7 +204,7 @@ static void ahci_pci_enable(AHCIQState *ahci)
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static void start_ahci_device(AHCIQState *ahci)
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{
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/* Map AHCI's ABAR (BAR5) */
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ahci->hba_base = qpci_iomap(ahci->dev, 5, &barsize);
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ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
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/* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
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qpci_device_enable(ahci->dev);
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@ -228,21 +226,23 @@ static void ahci_hba_enable(AHCIQState *ahci)
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* PxCMD.FR "FIS Receive Running"
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* PxCMD.CR "Command List Running"
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*/
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g_assert(ahci != NULL);
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uint32_t reg, ports_impl, clb, fb;
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uint16_t i;
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uint8_t num_cmd_slots;
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g_assert(ahci != NULL);
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/* Set GHC.AE to 1 */
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AHCI_SET(AHCI_GHC, AHCI_GHC_AE);
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reg = AHCI_RREG(AHCI_GHC);
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ASSERT_BIT_SET(reg, AHCI_GHC_AE);
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/* Cache CAP and CAP2. */
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ahci->cap = AHCI_RREG(AHCI_CAP);
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ahci->cap2 = AHCI_RREG(AHCI_CAP2);
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/* Read CAP.NCS, how many command slots do we have? */
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reg = AHCI_RREG(AHCI_CAP);
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num_cmd_slots = ((reg & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
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num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
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g_test_message("Number of Command Slots: %u", num_cmd_slots);
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/* Determine which ports are implemented. */
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@ -436,7 +436,7 @@ static void ahci_test_pci_spec(AHCIQState *ahci)
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/* Check specification adherence for capability extenstions. */
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data = qpci_config_readw(ahci->dev, datal);
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switch (ahci_fingerprint) {
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switch (ahci->fingerprint) {
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case AHCI_INTEL_ICH9:
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/* Intel ICH9 Family Datasheet 14.1.19 p.550 */
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g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
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@ -578,9 +578,8 @@ static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
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static void ahci_test_hba_spec(AHCIQState *ahci)
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{
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HBACap hcap;
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unsigned i;
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uint32_t cap, cap2, reg;
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uint32_t reg;
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uint32_t ports;
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uint8_t nports_impl;
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uint8_t maxports;
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@ -608,15 +607,15 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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*/
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/* 1 CAP - Capabilities Register */
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cap = AHCI_RREG(AHCI_CAP);
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ASSERT_BIT_CLEAR(cap, AHCI_CAP_RESERVED);
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ahci->cap = AHCI_RREG(AHCI_CAP);
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ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
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/* 2 GHC - Global Host Control */
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reg = AHCI_RREG(AHCI_GHC);
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ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
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ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
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ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
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if (BITSET(cap, AHCI_CAP_SAM)) {
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if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
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g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
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ASSERT_BIT_SET(reg, AHCI_GHC_AE);
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} else {
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@ -634,13 +633,13 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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g_assert_cmphex(ports, !=, 0);
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/* Ports Implemented must be <= Number of Ports. */
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nports_impl = ctpopl(ports);
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g_assert_cmpuint(((AHCI_CAP_NP & cap) + 1), >=, nports_impl);
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g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
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g_assert_cmphex(barsize, >, 0);
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/* Ports must be within the proper range. Given a mapping of SIZE,
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* 256 bytes are used for global HBA control, and the rest is used
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* for ports data, at 0x80 bytes each. */
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maxports = (barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
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g_assert_cmphex(ahci->barsize, >, 0);
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maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
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/* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
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g_assert_cmphex((reg >> maxports), ==, 0);
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@ -659,7 +658,7 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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/* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
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reg = AHCI_RREG(AHCI_CCCCTL);
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if (BITSET(cap, AHCI_CAP_CCCS)) {
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if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
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ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
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ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
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ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
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@ -675,13 +674,13 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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/* 8 EM_LOC */
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reg = AHCI_RREG(AHCI_EMLOC);
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if (BITCLR(cap, AHCI_CAP_EMS)) {
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if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
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g_assert_cmphex(reg, ==, 0);
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}
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/* 9 EM_CTL */
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reg = AHCI_RREG(AHCI_EMCTL);
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if (BITSET(cap, AHCI_CAP_EMS)) {
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if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
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ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
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ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
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ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
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@ -691,8 +690,8 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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}
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/* 10 CAP2 -- Capabilities Extended */
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cap2 = AHCI_RREG(AHCI_CAP2);
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ASSERT_BIT_CLEAR(cap2, AHCI_CAP2_RESERVED);
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ahci->cap2 = AHCI_RREG(AHCI_CAP2);
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ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
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/* 11 BOHC -- Bios/OS Handoff Control */
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reg = AHCI_RREG(AHCI_BOHC);
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@ -706,7 +705,7 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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}
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/* 24 -- 39: NVMHCI */
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if (BITCLR(cap2, AHCI_CAP2_NVMP)) {
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if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
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g_test_message("Verifying HBA/NVMHCI area is empty.");
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for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
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reg = AHCI_RREG(i);
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@ -722,12 +721,10 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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}
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/* 64 -- XX: Port Space */
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hcap.cap = cap;
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hcap.cap2 = cap2;
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for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
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if (BITSET(ports, 0x1)) {
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g_test_message("Testing port %u for spec", i);
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ahci_test_port_spec(ahci, &hcap, i);
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ahci_test_port_spec(ahci, i);
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} else {
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uint16_t j;
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uint16_t low = AHCI_PORTS + (32 * i);
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@ -746,8 +743,7 @@ static void ahci_test_hba_spec(AHCIQState *ahci)
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/**
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* Test the memory space for one port for specification adherence.
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*/
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static void ahci_test_port_spec(AHCIQState *ahci,
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HBACap *hcap, uint8_t port)
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static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
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{
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uint32_t reg;
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unsigned i;
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@ -757,7 +753,7 @@ static void ahci_test_port_spec(AHCIQState *ahci,
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
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/* (1) CLBU */
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if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
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if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
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reg = PX_RREG(port, AHCI_PX_CLBU);
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g_assert_cmphex(reg, ==, 0);
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}
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@ -767,7 +763,7 @@ static void ahci_test_port_spec(AHCIQState *ahci,
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ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
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/* (3) FBU */
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if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
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if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
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reg = PX_RREG(port, AHCI_PX_FBU);
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g_assert_cmphex(reg, ==, 0);
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}
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@ -803,7 +799,7 @@ static void ahci_test_port_spec(AHCIQState *ahci,
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
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}
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/* If we do not support MPS, MPSS and MPSP must be off. */
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if (BITCLR(hcap->cap, AHCI_CAP_SMPS)) {
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if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
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}
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@ -814,7 +810,7 @@ static void ahci_test_port_spec(AHCIQState *ahci,
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/* HPCP and ESP cannot both be active. */
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g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
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/* If CAP.FBSS is not set, FBSCP must not be set. */
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if (BITCLR(hcap->cap, AHCI_CAP_FBSS)) {
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if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
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}
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@ -874,7 +870,7 @@ static void ahci_test_port_spec(AHCIQState *ahci,
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ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
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if (BITSET(hcap->cap, AHCI_CAP_FBSS)) {
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if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
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/* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
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g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
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}
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@ -249,6 +249,10 @@ typedef struct AHCIQState {
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QOSState *parent;
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QPCIDevice *dev;
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void *hba_base;
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uint64_t barsize;
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uint32_t fingerprint;
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uint32_t cap;
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uint32_t cap2;
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} AHCIQState;
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/**
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@ -340,11 +344,6 @@ typedef struct PRD {
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uint32_t dbc; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
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} PRD;
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typedef struct HBACap {
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uint32_t cap;
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uint32_t cap2;
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} HBACap;
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/*** Macro Utilities ***/
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#define BITANY(data, mask) (((data) & (mask)) != 0)
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#define BITSET(data, mask) (((data) & (mask)) == (mask))
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