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target/riscv: Remove gen_system()

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with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:54:08 -08:00
parent 8dc9e8a8b0
commit 8f7bc27386
1 changed files with 0 additions and 34 deletions
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34
target/riscv/translate.c
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@ -473,33 +473,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int csr)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
switch (opc) {
case OPC_RISC_ECALL:
switch (csr) {
case 0x0: /* ECALL */
/* always generates U-level ECALL, fixed in do_interrupt handler */
generate_exception(ctx, RISCV_EXCP_U_ECALL);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
case 0x1: /* EBREAK */
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
gen_exception_illegal(ctx);
break;
}
break;
}
}
static void decode_RV32_64C0(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@ -680,7 +653,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(DisasContext *ctx)
{
int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@ -689,14 +661,8 @@ static void decode_RV32_64G(DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
rd = GET_RD(ctx->opcode);
switch (op) {
case OPC_RISC_SYSTEM:
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
default:
gen_exception_illegal(ctx);
break;