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https://github.com/xemu-project/xemu.git
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Add common keys to firmware configuration
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5260 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
084a197a20
commit
905fdcb526
@ -259,6 +259,7 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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{
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FWCfgState *s;
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int io_ctl_memory, io_data_memory;
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extern int nographic;
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s = qemu_mallocz(sizeof(FWCfgState));
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if (!s)
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@ -283,6 +284,9 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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}
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fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
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fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
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fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)nographic);
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fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
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register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
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qemu_register_reset(fw_cfg_reset, s);
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fw_cfg_reset(s);
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@ -4,6 +4,10 @@
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#define FW_CFG_SIGNATURE 0x00
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#define FW_CFG_ID 0x01
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#define FW_CFG_UUID 0x02
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#define FW_CFG_RAM_SIZE 0x03
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#define FW_CFG_NOGRAPHIC 0x04
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#define FW_CFG_NB_CPUS 0x05
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#define FW_CFG_MACHINE_ID 0x06
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#define FW_CFG_MAX_ENTRY 0x10
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#define FW_CFG_WRITE_CHANNEL 0x4000
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1
hw/pc.c
1
hw/pc.c
@ -433,6 +433,7 @@ static void bochs_bios_init(void)
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fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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}
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/* Generate an initial boot sector which sets state and jump to
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77
hw/sun4m.c
77
hw/sun4m.c
@ -101,7 +101,8 @@ struct hwdef {
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// register bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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int machine_id; // For NVRAM
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint32_t iommu_version;
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uint32_t intbit_to_level[32];
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uint64_t max_mem;
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@ -122,7 +123,8 @@ struct sun4d_hwdef {
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// IRQ numbers are not PIL ones, but SBI register bit numbers
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int esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, me_irq;
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int machine_id; // For NVRAM
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint32_t iounit_version;
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uint64_t max_mem;
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const char * const default_cpu_model;
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@ -178,7 +180,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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const char *boot_devices, ram_addr_t RAM_size,
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uint32_t kernel_size,
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int width, int height, int depth,
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int machine_id, const char *arch)
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int nvram_machine_id, const char *arch)
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{
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unsigned int i;
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uint32_t start, end;
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@ -251,7 +253,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
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nvram_machine_id);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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@ -568,7 +571,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
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graphic_height, graphic_depth, hwdef->nvram_machine_id,
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"Sun4m");
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if (hwdef->ecc_base != (target_phys_addr_t)-1)
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ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
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@ -576,6 +580,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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}
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static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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@ -721,12 +727,30 @@ static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
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graphic_height, graphic_depth, hwdef->nvram_machine_id,
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"Sun4c");
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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}
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enum {
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ss2_id = 0,
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ss5_id = 32,
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vger_id,
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lx_id,
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ss4_id,
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scls_id,
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sbook_id,
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ss10_id = 64,
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ss20_id,
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ss600mp_id,
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ss1000_id = 96,
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ss2000_id,
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};
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static const struct hwdef hwdefs[] = {
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/* SS-5 */
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{
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@ -761,7 +785,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = 5,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = ss5_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -805,7 +830,8 @@ static const struct hwdef hwdefs[] = {
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.me_irq = 30,
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.cs_irq = -1,
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.ecc_irq = 28,
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.machine_id = 0x72,
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.nvram_machine_id = 0x72,
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.machine_id = ss10_id,
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.iommu_version = 0x03000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -849,7 +875,8 @@ static const struct hwdef hwdefs[] = {
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.me_irq = 30,
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.cs_irq = -1,
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.ecc_irq = 28,
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.machine_id = 0x71,
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.nvram_machine_id = 0x71,
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.machine_id = ss600mp_id,
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.iommu_version = 0x01000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -893,7 +920,8 @@ static const struct hwdef hwdefs[] = {
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.me_irq = 30,
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.cs_irq = -1,
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.ecc_irq = 28,
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.machine_id = 0x72,
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.nvram_machine_id = 0x72,
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.machine_id = ss20_id,
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.iommu_version = 0x13000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -933,7 +961,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 1,
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.me_irq = 1,
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.cs_irq = -1,
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.machine_id = 0x55,
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.nvram_machine_id = 0x55,
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.machine_id = ss2_id,
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.max_mem = 0x10000000,
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.default_cpu_model = "Cypress CY7C601",
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},
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@ -970,7 +999,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = vger_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -1012,7 +1042,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = lx_id,
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.iommu_version = 0x04000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -1054,7 +1085,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = 5,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = ss4_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -1096,7 +1128,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = scls_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -1138,7 +1171,8 @@ static const struct hwdef hwdefs[] = {
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = -1,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = sbook_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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@ -1359,7 +1393,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
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.clock1_irq = 10,
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.ms_kb_irq = 12,
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.ser_irq = 12,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = ss1000_id,
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.iounit_version = 0x03000000,
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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@ -1392,7 +1427,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
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.clock1_irq = 10,
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.ms_kb_irq = 12,
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.ser_irq = 12,
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.machine_id = 0x80,
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.nvram_machine_id = 0x80,
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.machine_id = ss2000_id,
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.iounit_version = 0x03000000,
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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@ -1538,10 +1574,13 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
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graphic_height, graphic_depth, hwdef->nvram_machine_id,
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"Sun4d");
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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}
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/* SPARCserver 1000 hardware initialisation */
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10
hw/sun4u.c
10
hw/sun4u.c
@ -49,6 +49,7 @@
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struct hwdef {
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const char * const default_cpu_model;
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uint16_t machine_id;
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};
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int DMA_get_channel_mode (int nchan)
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@ -420,16 +421,25 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
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fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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}
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enum {
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sun4u_id = 0,
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sun4v_id = 64,
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};
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static const struct hwdef hwdefs[] = {
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/* Sun4u generic PC-like machine */
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{
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.default_cpu_model = "TI UltraSparc II",
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.machine_id = sun4u_id,
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},
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/* Sun4v generic PC-like machine */
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{
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.default_cpu_model = "Sun UltraSparc T1",
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.machine_id = sun4v_id,
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},
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};
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