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acpi: build_dmar_q35: use acpi_table_begin()/acpi_table_end() instead of build_header()
it replaces error-prone pointer arithmetic for build_header() API, with 2 calls to start and finish table creation, which hides offsets magic from API user. While at it switch to build_append_int_noprefix() to build table entries tables. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20210924122802.1455362-19-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov
Michael S. Tsirkin
parent
e5b6d55a6e
commit
91a6b97569
@ -2086,8 +2086,9 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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static void
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insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
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{
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const size_t device_scope_size = 6 /* device scope structure */ +
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2 /* 1 path entry */;
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GArray *scope_blob = opaque;
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AcpiDmarDeviceScope *scope = NULL;
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if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
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/* Dmar Scope Type: 0x02 for PCI Bridge */
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@ -2098,8 +2099,7 @@ insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
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}
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/* length */
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build_append_int_noprefix(scope_blob,
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sizeof(*scope) + sizeof(scope->path[0]), 1);
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build_append_int_noprefix(scope_blob, device_scope_size, 1);
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/* reserved */
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build_append_int_noprefix(scope_blob, 0, 2);
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/* enumeration_id */
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@ -2131,26 +2131,26 @@ dmar_host_bridges(Object *obj, void *opaque)
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}
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/*
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* VT-d spec 8.1 DMA Remapping Reporting Structure
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* (version Oct. 2014 or later)
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* Intel ® Virtualization Technology for Directed I/O
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* Architecture Specification. Revision 3.3
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* 8.1 DMA Remapping Reporting Structure
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*/
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static void
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build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
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const char *oem_table_id)
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{
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int dmar_start = table_data->len;
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AcpiTableDmar *dmar;
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AcpiDmarHardwareUnit *drhd;
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AcpiDmarRootPortATS *atsr;
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uint8_t dmar_flags = 0;
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uint8_t rsvd10[10] = {};
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/* Root complex IOAPIC uses one path only */
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const size_t ioapic_scope_size = 6 /* device scope structure */ +
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2 /* 1 path entry */;
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X86IOMMUState *iommu = x86_iommu_get_default();
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AcpiDmarDeviceScope *scope = NULL;
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/* Root complex IOAPIC use one path[0] only */
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size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
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IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
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GArray *scope_blob = g_array_new(false, true, 1);
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AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
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.oem_table_id = oem_table_id };
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/*
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* A PCI bus walk, for each PCI host bridge.
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* Insert scope for each PCI bridge and endpoint device which
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@ -2164,43 +2164,52 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
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dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
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}
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dmar = acpi_data_push(table_data, sizeof(*dmar));
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dmar->host_address_width = intel_iommu->aw_bits - 1;
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dmar->flags = dmar_flags;
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acpi_table_begin(&table, table_data);
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/* Host Address Width */
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build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
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build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
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g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
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/* DMAR Remapping Hardware Unit Definition structure */
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drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
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drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
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drhd->length =
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cpu_to_le16(sizeof(*drhd) + ioapic_scope_size + scope_blob->len);
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drhd->flags = 0; /* Don't include all pci device */
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drhd->pci_segment = cpu_to_le16(0);
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drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
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/* 8.3 DMAR Remapping Hardware Unit Definition structure */
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build_append_int_noprefix(table_data, 0, 2); /* Type */
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/* Length */
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build_append_int_noprefix(table_data,
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16 + ioapic_scope_size + scope_blob->len, 2);
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/* Flags */
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build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
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1);
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build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
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build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
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/* Register Base Address */
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build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
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/* Scope definition for the root-complex IOAPIC. See VT-d spec
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* 8.3.1 (version Oct. 2014 or later). */
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scope = &drhd->scope[0];
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scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
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scope->length = ioapic_scope_size;
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scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
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scope->bus = Q35_PSEUDO_BUS_PLATFORM;
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scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
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scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
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build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
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build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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/* Enumeration ID */
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build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
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/* Start Bus Number */
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build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
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/* Path, {Device, Function} pair */
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build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
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build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
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/* Add scope found above */
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g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
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g_array_free(scope_blob, true);
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if (iommu->dt_supported) {
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atsr = acpi_data_push(table_data, sizeof(*atsr));
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atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
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atsr->length = cpu_to_le16(sizeof(*atsr));
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atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
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atsr->pci_segment = cpu_to_le16(0);
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/* 8.5 Root Port ATS Capability Reporting Structure */
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build_append_int_noprefix(table_data, 2, 2); /* Type */
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build_append_int_noprefix(table_data, 8, 2); /* Length */
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build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
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build_append_int_noprefix(table_data, 0, 1); /* Reserved */
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build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
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}
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build_header(linker, table_data, (void *)(table_data->data + dmar_start),
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"DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
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acpi_table_end(linker, &table);
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}
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/*
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@ -358,74 +358,6 @@ struct AcpiGenericTimerTable {
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} QEMU_PACKED;
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typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
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/* DMAR - DMA Remapping table r2.2 */
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struct AcpiTableDmar {
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ACPI_TABLE_HEADER_DEF
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uint8_t host_address_width; /* Maximum DMA physical addressability */
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uint8_t flags;
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uint8_t reserved[10];
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} QEMU_PACKED;
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typedef struct AcpiTableDmar AcpiTableDmar;
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/* Masks for Flags field above */
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#define ACPI_DMAR_INTR_REMAP 1
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#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
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/* Values for sub-structure type for DMAR */
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enum {
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ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
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ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
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ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
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ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
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ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
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ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
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};
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/*
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* Sub-structures for DMAR
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*/
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/* Device scope structure for DRHD. */
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struct AcpiDmarDeviceScope {
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uint8_t entry_type;
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uint8_t length;
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uint16_t reserved;
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uint8_t enumeration_id;
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uint8_t bus;
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struct {
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uint8_t device;
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uint8_t function;
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} path[];
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} QEMU_PACKED;
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typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
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/* Type 0: Hardware Unit Definition */
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struct AcpiDmarHardwareUnit {
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uint16_t type;
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uint16_t length;
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uint8_t flags;
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uint8_t reserved;
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uint16_t pci_segment; /* The PCI Segment associated with this unit */
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uint64_t address; /* Base address of remapping hardware register-set */
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AcpiDmarDeviceScope scope[];
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} QEMU_PACKED;
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typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
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/* Type 2: Root Port ATS Capability Reporting Structure */
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struct AcpiDmarRootPortATS {
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uint16_t type;
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uint16_t length;
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uint8_t flags;
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uint8_t reserved;
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uint16_t pci_segment;
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AcpiDmarDeviceScope scope[];
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} QEMU_PACKED;
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typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
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/* Masks for Flags field above */
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#define ACPI_DMAR_INCLUDE_PCI_ALL 1
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#define ACPI_DMAR_ATSR_ALL_PORTS 1
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/*
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* Input Output Remapping Table (IORT)
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* Conforms to "IO Remapping Table System Software on ARM Platforms",
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