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https://github.com/xemu-project/xemu.git
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Improved debug output for the MIPS opcode decoder.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2801 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
4759513bd9
commit
923617a396
@ -540,7 +540,7 @@ enum {
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BS_EXCP = 3, /* We reached an exception condition */
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};
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#if defined MIPS_DEBUG_DISAS
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#ifdef MIPS_DEBUG_DISAS
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#define MIPS_DEBUG(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_TB_IN_ASM) { \
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@ -710,7 +710,7 @@ OP_ST_TABLE(uxc1);
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static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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int base, int16_t offset)
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{
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const char *opn = "unk";
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const char *opn = "ldst";
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if (base == 0) {
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GEN_LOAD_IMM_TN(T0, offset);
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@ -849,7 +849,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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opn = "sc";
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break;
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default:
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MIPS_INVAL("load/store");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -860,7 +860,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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int base, int16_t offset)
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{
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const char *opn = "unk";
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const char *opn = "flt_ldst";
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if (base == 0) {
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GEN_LOAD_IMM_TN(T0, offset);
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@ -896,7 +896,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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opn = "sdc1";
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break;
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default:
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MIPS_INVAL("float load/store");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -908,7 +908,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
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int rs, int16_t imm)
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{
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uint32_t uimm;
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const char *opn = "unk";
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const char *opn = "imm arith";
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if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
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/* if no destination, treat it as a NOP
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@ -1073,7 +1073,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
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break;
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#endif
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default:
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MIPS_INVAL("imm arith");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1085,7 +1085,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
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static void gen_arith (DisasContext *ctx, uint32_t opc,
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int rd, int rs, int rt)
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{
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const char *opn = "unk";
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const char *opn = "arith";
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if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
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&& opc != OPC_DADD && opc != OPC_DSUB) {
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@ -1223,7 +1223,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
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break;
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#endif
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default:
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MIPS_INVAL("arith");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1235,7 +1235,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc,
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/* Arithmetic on HI/LO registers */
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static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
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{
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const char *opn = "unk";
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const char *opn = "hilo";
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if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
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/* Treat as a NOP */
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@ -1264,7 +1264,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
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opn = "mtlo";
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break;
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default:
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MIPS_INVAL("HILO");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1274,7 +1274,7 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
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static void gen_muldiv (DisasContext *ctx, uint32_t opc,
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int rs, int rt)
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{
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const char *opn = "unk";
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const char *opn = "mul/div";
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GEN_LOAD_REG_TN(T0, rs);
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GEN_LOAD_REG_TN(T1, rt);
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@ -1330,7 +1330,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
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opn = "msubu";
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break;
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default:
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MIPS_INVAL("mul/div");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1340,7 +1340,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
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static void gen_cl (DisasContext *ctx, uint32_t opc,
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int rd, int rs)
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{
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const char *opn = "unk";
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const char *opn = "CLx";
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if (rd == 0) {
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/* Treat as a NOP */
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MIPS_DEBUG("NOP");
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@ -1367,7 +1367,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
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break;
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#endif
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default:
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MIPS_INVAL("CLx");
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1431,7 +1431,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
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/* Never trap: treat as NOP */
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return;
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default:
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MIPS_INVAL("TRAP");
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MIPS_INVAL("trap");
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1462,7 +1462,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
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gen_op_ne();
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break;
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default:
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MIPS_INVAL("TRAP");
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MIPS_INVAL("trap");
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1499,12 +1499,13 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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int bcond = 0;
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile,
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"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
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ctx->pc);
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}
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MIPS_INVAL("branch/jump in bdelay slot");
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#endif
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1553,6 +1554,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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if (offset != 0 && offset != 16) {
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/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
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others are reserved. */
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MIPS_INVAL("jump hint");
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -1610,12 +1612,12 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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return;
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case OPC_J:
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("j %08x", btarget);
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MIPS_DEBUG("j " TARGET_FMT_lx, btarget);
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break;
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case OPC_JAL:
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blink = 31;
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ctx->hflags |= MIPS_HFLAG_B;
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MIPS_DEBUG("jal %08x", btarget);
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MIPS_DEBUG("jal " TARGET_FMT_lx, btarget);
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break;
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case OPC_JR:
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ctx->hflags |= MIPS_HFLAG_BR;
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@ -1635,70 +1637,70 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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switch (opc) {
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case OPC_BEQ:
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gen_op_eq();
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MIPS_DEBUG("beq %s, %s, %08x",
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MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
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regnames[rs], regnames[rt], btarget);
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goto not_likely;
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case OPC_BEQL:
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gen_op_eq();
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MIPS_DEBUG("beql %s, %s, %08x",
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MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
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regnames[rs], regnames[rt], btarget);
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goto likely;
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case OPC_BNE:
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gen_op_ne();
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MIPS_DEBUG("bne %s, %s, %08x",
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MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
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regnames[rs], regnames[rt], btarget);
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goto not_likely;
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case OPC_BNEL:
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gen_op_ne();
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MIPS_DEBUG("bnel %s, %s, %08x",
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MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
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regnames[rs], regnames[rt], btarget);
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goto likely;
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case OPC_BGEZ:
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gen_op_gez();
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MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto not_likely;
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case OPC_BGEZL:
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gen_op_gez();
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MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto likely;
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case OPC_BGEZAL:
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gen_op_gez();
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MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
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blink = 31;
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goto not_likely;
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case OPC_BGEZALL:
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gen_op_gez();
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blink = 31;
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MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto likely;
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case OPC_BGTZ:
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gen_op_gtz();
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MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto not_likely;
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case OPC_BGTZL:
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gen_op_gtz();
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MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto likely;
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case OPC_BLEZ:
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gen_op_lez();
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MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto not_likely;
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case OPC_BLEZL:
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gen_op_lez();
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MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto likely;
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case OPC_BLTZ:
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gen_op_ltz();
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MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto not_likely;
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case OPC_BLTZL:
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gen_op_ltz();
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MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
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goto likely;
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case OPC_BLTZAL:
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gen_op_ltz();
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blink = 31;
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MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
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not_likely:
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ctx->hflags |= MIPS_HFLAG_BC;
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gen_op_set_bcond();
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@ -1706,7 +1708,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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case OPC_BLTZALL:
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gen_op_ltz();
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blink = 31;
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MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
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MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
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likely:
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ctx->hflags |= MIPS_HFLAG_BL;
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gen_op_set_bcond();
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@ -1718,7 +1720,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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return;
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}
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}
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MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
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MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
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blink, ctx->hflags, btarget);
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ctx->btarget = btarget;
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if (blink > 0) {
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@ -4221,6 +4223,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
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case OPC_DERET:
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opn = "deret";
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if (!(ctx->hflags & MIPS_HFLAG_DM)) {
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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} else {
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save_cpu_state(ctx, 0);
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@ -4238,11 +4241,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
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ctx->bstate = BS_EXCP;
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break;
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default:
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
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ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
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((ctx->opcode >> 16) & 0x1F));
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}
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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return;
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}
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@ -4254,25 +4253,26 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
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int32_t cc, int32_t offset)
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{
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target_ulong btarget;
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const char *opn = "cp1 cond branch";
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btarget = ctx->pc + 4 + offset;
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switch (op) {
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case OPC_BC1F:
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gen_op_bc1f(cc);
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MIPS_DEBUG("bc1f " TARGET_FMT_lx, btarget);
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opn = "bc1f";
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goto not_likely;
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case OPC_BC1FL:
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gen_op_bc1f(cc);
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MIPS_DEBUG("bc1fl " TARGET_FMT_lx, btarget);
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opn = "bc1fl";
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goto likely;
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case OPC_BC1T:
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gen_op_bc1t(cc);
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MIPS_DEBUG("bc1t " TARGET_FMT_lx, btarget);
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opn = "bc1t";
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goto not_likely;
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case OPC_BC1TL:
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gen_op_bc1t(cc);
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MIPS_DEBUG("bc1tl " TARGET_FMT_lx, btarget);
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opn = "bc1tl";
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likely:
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ctx->hflags |= MIPS_HFLAG_BL;
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gen_op_set_bcond();
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@ -4280,34 +4280,31 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
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break;
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case OPC_BC1FANY2:
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gen_op_bc1fany2(cc);
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MIPS_DEBUG("bc1fany2 " TARGET_FMT_lx, btarget);
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opn = "bc1fany2";
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goto not_likely;
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case OPC_BC1TANY2:
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gen_op_bc1tany2(cc);
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MIPS_DEBUG("bc1tany2 " TARGET_FMT_lx, btarget);
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opn = "bc1tany2";
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goto not_likely;
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case OPC_BC1FANY4:
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gen_op_bc1fany4(cc);
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MIPS_DEBUG("bc1fany4 " TARGET_FMT_lx, btarget);
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opn = "bc1fany4";
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goto not_likely;
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case OPC_BC1TANY4:
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gen_op_bc1tany4(cc);
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MIPS_DEBUG("bc1tany4 " TARGET_FMT_lx, btarget);
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opn = "bc1tany4";
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not_likely:
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ctx->hflags |= MIPS_HFLAG_BC;
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gen_op_set_bcond();
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break;
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default:
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MIPS_INVAL("cp1 branch");
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MIPS_INVAL(opn);
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generate_exception (ctx, EXCP_RI);
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return;
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}
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MIPS_DEBUG("enter ds: cond %02x target " TARGET_FMT_lx,
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MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
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ctx->hflags, btarget);
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ctx->btarget = btarget;
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return;
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}
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/* Coprocessor 1 (FPU) */
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@ -4325,18 +4322,19 @@ static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
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* FIXME: This is broken for R2, it needs to be checked at runtime, not
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* at translation time.
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*/
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#define CHECK_FR(ctx, freg) do { \
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#define CHECK_FR(ctx, freg) do { \
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if (!((ctx)->CP0_Status & (1 << CP0St_FR)) && ((freg) & 1)) { \
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generate_exception (ctx, EXCP_RI); \
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return; \
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} \
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MIPS_INVAL("FPU mode"); \
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generate_exception (ctx, EXCP_RI); \
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return; \
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} \
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} while(0)
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#define FOP(func, fmt) (((fmt) << 21) | (func))
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|
||||
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
|
||||
{
|
||||
const char *opn = "unk";
|
||||
const char *opn = "cp1 move";
|
||||
|
||||
switch (opc) {
|
||||
case OPC_MFC1:
|
||||
@ -4390,11 +4388,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
|
||||
opn = "mthc1";
|
||||
break;
|
||||
default:
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||
fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
|
||||
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
|
||||
((ctx->opcode >> 16) & 0x1F));
|
||||
}
|
||||
MIPS_INVAL(opn);
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
return;
|
||||
}
|
||||
@ -4440,7 +4434,7 @@ GEN_MOVCF(ps);
|
||||
static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
|
||||
int fs, int fd, int cc)
|
||||
{
|
||||
const char *opn = "unk";
|
||||
const char *opn = "farith";
|
||||
const char *condnames[] = {
|
||||
"c.f",
|
||||
"c.un",
|
||||
@ -5041,11 +5035,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
|
||||
opn = condnames[func-48];
|
||||
break;
|
||||
default:
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||
fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
|
||||
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
|
||||
((ctx->opcode >> 16) & 0x1F));
|
||||
}
|
||||
MIPS_INVAL(opn);
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
return;
|
||||
}
|
||||
@ -5059,7 +5049,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
|
||||
static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
|
||||
int base, int index)
|
||||
{
|
||||
const char *opn = "unk";
|
||||
const char *opn = "extended float load/store";
|
||||
|
||||
GEN_LOAD_REG_TN(T0, base);
|
||||
GEN_LOAD_REG_TN(T1, index);
|
||||
@ -5098,7 +5088,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
|
||||
opn = "suxc1";
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("extended float load/store");
|
||||
MIPS_INVAL(opn);
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
return;
|
||||
}
|
||||
@ -5108,7 +5098,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
|
||||
static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
|
||||
int fr, int fs, int ft)
|
||||
{
|
||||
const char *opn = "unk";
|
||||
const char *opn = "flt3_arith";
|
||||
|
||||
/* All of those work only on 64bit FPUs. */
|
||||
CHECK_FR(ctx, fd | fr | fs | ft);
|
||||
@ -5173,11 +5163,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
opn = "nmsub.ps";
|
||||
break;
|
||||
default:
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||
fprintf(logfile, "Invalid extended FP arith function: %08x %03x %03x\n",
|
||||
ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F);
|
||||
}
|
||||
default:
|
||||
MIPS_INVAL(opn);
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
return;
|
||||
}
|
||||
@ -5459,7 +5446,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
/* treat as noop */
|
||||
break;
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("REGIMM");
|
||||
MIPS_INVAL("regimm");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5494,7 +5481,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
ctx->bstate = BS_STOP;
|
||||
break;
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("MFMC0");
|
||||
MIPS_INVAL("mfmc0");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5506,10 +5493,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
/* Shadow registers not implemented. */
|
||||
GEN_LOAD_REG_TN(T0, rt);
|
||||
GEN_STORE_TN_REG(rd, T0);
|
||||
} else
|
||||
} else {
|
||||
MIPS_INVAL("shadow register move");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("cp0");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5539,7 +5529,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
/* Treat as a noop */
|
||||
break;
|
||||
|
||||
/* Floating point. */
|
||||
/* Floating point (COP1). */
|
||||
case OPC_LWC1:
|
||||
case OPC_LDC1:
|
||||
case OPC_SWC1:
|
||||
@ -5584,6 +5574,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
(imm >> 8) & 0x7);
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("cp1");
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5635,6 +5626,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("cp3");
|
||||
generate_exception (ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5667,7 +5659,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
|
||||
/* MDMX: Not implemented. */
|
||||
#endif
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("");
|
||||
MIPS_INVAL("major opcode");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
@ -5764,7 +5756,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
|
||||
cpu_dump_state(env, logfile, fprintf, 0);
|
||||
}
|
||||
#endif
|
||||
#if defined MIPS_DEBUG_DISAS
|
||||
#ifdef MIPS_DEBUG_DISAS
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM)
|
||||
fprintf(logfile, "\ntb %p super %d cond %04x\n",
|
||||
tb, ctx.mem_idx, ctx.hflags);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user