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RISC-V: Convert trap debugging to trace events

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Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2019-03-16 01:21:12 +00:00 committed by Palmer Dabbelt
parent acbbb94e57
commit 929f0a7fc4
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
3 changed files with 6 additions and 9 deletions
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1
Makefile.objs
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@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa
trace-events-subdirs += target/i386
trace-events-subdirs += target/mips
trace-events-subdirs += target/ppc
trace-events-subdirs += target/riscv
trace-events-subdirs += target/s390x
trace-events-subdirs += target/sparc
trace-events-subdirs += ui

12
target/riscv/cpu_helper.c
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@ -22,8 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#define RISCV_DEBUG_INTERRUPT 0
#include "trace.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
if (RISCV_DEBUG_INTERRUPT) {
qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
"epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
env->mhartid, async ? "intr" : "trap",
(async ? riscv_intr_names : riscv_excp_names)[cause],
env->pc, tval);
}
trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ?
(async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {

2
target/riscv/trace-events Normal file
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@ -0,0 +1,2 @@
# target/riscv/cpu_helper.c
riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"