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target/arm: Swap PMU values before/after migrations
Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1459,11 +1459,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
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.access = PL0_RW, .accessfn = pmreg_access_ccntr,
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.type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write, },
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.fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
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.readfn = pmccntr_read, .writefn = pmccntr_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write, },
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#endif
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{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
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.writefn = pmccfiltr_write,
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.writefn = pmccfiltr_write, .raw_writefn = raw_write,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
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@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque)
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{
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ARMCPU *cpu = opaque;
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if (!kvm_enabled()) {
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pmu_op_start(&cpu->env);
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}
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if (kvm_enabled()) {
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if (!write_kvmstate_to_list(cpu)) {
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/* This should never fail */
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@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque)
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return 0;
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}
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static int cpu_post_save(void *opaque)
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{
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ARMCPU *cpu = opaque;
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if (!kvm_enabled()) {
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pmu_op_finish(&cpu->env);
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}
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return 0;
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}
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static int cpu_pre_load(void *opaque)
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{
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ARMCPU *cpu = opaque;
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@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque)
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*/
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env->irq_line_state = UINT32_MAX;
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if (!kvm_enabled()) {
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pmu_op_start(&cpu->env);
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}
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return 0;
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}
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@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id)
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hw_breakpoint_update_all(cpu);
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hw_watchpoint_update_all(cpu);
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if (!kvm_enabled()) {
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pmu_op_finish(&cpu->env);
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}
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return 0;
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}
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@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu = {
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.version_id = 22,
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.minimum_version_id = 22,
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.pre_save = cpu_pre_save,
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.post_save = cpu_post_save,
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.pre_load = cpu_pre_load,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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