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target/arm: Convert "double-precision" register moves to decodetree
Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
160f3b64c5
commit
9851ed9269
@ -475,3 +475,150 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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return true;
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}
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static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
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{
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/* VMOV scalar to general purpose register */
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TCGv_i32 tmp;
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int pass;
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uint32_t offset;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
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return false;
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}
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offset = a->index << a->size;
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pass = extract32(offset, 2, 1);
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offset = extract32(offset, 0, 2) * 8;
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if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = neon_load_reg(a->vn, pass);
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switch (a->size) {
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case 0:
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if (offset) {
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tcg_gen_shri_i32(tmp, tmp, offset);
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}
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if (a->u) {
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gen_uxtb(tmp);
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} else {
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gen_sxtb(tmp);
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}
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break;
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case 1:
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if (a->u) {
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if (offset) {
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tcg_gen_shri_i32(tmp, tmp, 16);
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} else {
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gen_uxth(tmp);
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}
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} else {
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if (offset) {
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tcg_gen_sari_i32(tmp, tmp, 16);
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} else {
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gen_sxth(tmp);
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}
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}
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break;
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case 2:
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break;
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}
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store_reg(s, a->rt, tmp);
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return true;
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}
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static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
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{
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/* VMOV general purpose register to scalar */
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TCGv_i32 tmp, tmp2;
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int pass;
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uint32_t offset;
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
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return false;
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}
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offset = a->index << a->size;
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pass = extract32(offset, 2, 1);
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offset = extract32(offset, 0, 2) * 8;
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if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = load_reg(s, a->rt);
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switch (a->size) {
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case 0:
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tmp2 = neon_load_reg(a->vn, pass);
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tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
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tcg_temp_free_i32(tmp2);
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break;
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case 1:
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tmp2 = neon_load_reg(a->vn, pass);
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tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
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tcg_temp_free_i32(tmp2);
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break;
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case 2:
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break;
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}
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neon_store_reg(a->vn, pass, tmp);
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return true;
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}
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static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
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{
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/* VDUP (general purpose register) */
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TCGv_i32 tmp;
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int size, vec_size;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
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return false;
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}
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if (a->b && a->e) {
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return false;
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}
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if (a->q && (a->vn & 1)) {
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return false;
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}
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vec_size = a->q ? 16 : 8;
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if (a->b) {
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size = 0;
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} else if (a->e) {
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size = 1;
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} else {
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size = 2;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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tmp = load_reg(s, a->rt);
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tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
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vec_size, vec_size, tmp);
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tcg_temp_free_i32(tmp);
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return true;
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}
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@ -3151,87 +3151,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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/* single register transfer */
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rd = (insn >> 12) & 0xf;
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if (dp) {
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int size;
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int pass;
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VFP_DREG_N(rn, insn);
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if (insn & 0xf)
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return 1;
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if (insn & 0x00c00060
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&& !arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return 1;
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}
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pass = (insn >> 21) & 1;
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if (insn & (1 << 22)) {
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size = 0;
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offset = ((insn >> 5) & 3) * 8;
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} else if (insn & (1 << 5)) {
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size = 1;
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offset = (insn & (1 << 6)) ? 16 : 0;
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} else {
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size = 2;
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offset = 0;
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}
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if (insn & ARM_CP_RW_BIT) {
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/* vfp->arm */
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tmp = neon_load_reg(rn, pass);
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switch (size) {
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case 0:
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if (offset)
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tcg_gen_shri_i32(tmp, tmp, offset);
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if (insn & (1 << 23))
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gen_uxtb(tmp);
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else
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gen_sxtb(tmp);
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break;
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case 1:
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if (insn & (1 << 23)) {
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if (offset) {
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tcg_gen_shri_i32(tmp, tmp, 16);
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} else {
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gen_uxth(tmp);
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}
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} else {
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if (offset) {
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tcg_gen_sari_i32(tmp, tmp, 16);
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} else {
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gen_sxth(tmp);
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}
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}
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break;
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case 2:
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break;
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}
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store_reg(s, rd, tmp);
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} else {
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/* arm->vfp */
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tmp = load_reg(s, rd);
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if (insn & (1 << 23)) {
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/* VDUP */
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int vec_size = pass ? 16 : 8;
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tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0),
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vec_size, vec_size, tmp);
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tcg_temp_free_i32(tmp);
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} else {
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/* VMOV */
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switch (size) {
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case 0:
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tmp2 = neon_load_reg(rn, pass);
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tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
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tcg_temp_free_i32(tmp2);
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break;
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case 1:
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tmp2 = neon_load_reg(rn, pass);
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tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
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tcg_temp_free_i32(tmp2);
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break;
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case 2:
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break;
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}
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neon_store_reg(rn, pass, tmp);
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}
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}
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/* already handled by decodetree */
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return 1;
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} else { /* !dp */
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bool is_sysreg;
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@ -26,3 +26,39 @@
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# 1110 1110 .... .... .... 101. .... ....
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# (but those patterns might also cover some Neon instructions,
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# which do not live in this file.)
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# VFP registers have an odd encoding with a four-bit field
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# and a one-bit field which are assembled in different orders
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# depending on whether the register is double or single precision.
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# Each individual instruction function must do the checks for
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# "double register selected but CPU does not have double support"
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# and "double register number has bit 4 set but CPU does not
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# support D16-D31" (which should UNDEF).
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%vm_dp 5:1 0:4
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%vm_sp 0:4 5:1
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%vn_dp 7:1 16:4
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%vn_sp 16:4 7:1
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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%vmov_idx_b 21:1 5:2
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%vmov_idx_h 21:1 6:1
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# VMOV scalar to general-purpose register; note that this does
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# include some Neon cases.
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VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2 u=0
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VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2
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VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
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vn=%vn_dp
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