xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-24 03:59:52 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M

Browse Source 
The FPDSCR register has a similar layout to the FPSCR.  In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4).  Update the reset value and the code
that handles writes to this register accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-11-19 21:56:04 +00:00
parent 64f863baee
commit 99c7834fba
3 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
hw/intc/armv7m_nvic.c
View File

@ -2068,7 +2068,14 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
break;
case 0xf3c: /* FPDSCR */
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= 0x07c00000;
uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK;
if (cpu_isar_feature(any_fp16, cpu)) {
mask |= FPCR_FZ16;
}
value &= mask;
if (cpu_isar_feature(aa32_lob, cpu)) {
value |= 4 << FPCR_LTPSIZE_SHIFT;
}
cpu->env.v7m.fpdscr[attrs.secure] = value;
}
break;

3
target/arm/cpu.c
View File

@ -262,6 +262,9 @@ static void arm_cpu_reset(DeviceState *dev)
* always reset to 4.
*/
env->v7m.ltpsize = 4;
/* The LTPSIZE field in FPDSCR is constant and reads as 4. */
env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
}
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

5
target/arm/cpu.h
View File

@ -1521,14 +1521,19 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
#define FPCR_AHP (1 << 26) /* Alternative half-precision */
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
#define FPCR_V (1 << 28) /* FP overflow flag */
#define FPCR_C (1 << 29) /* FP carry flag */
#define FPCR_Z (1 << 30) /* FP zero flag */
#define FPCR_N (1 << 31) /* FP negative flag */
#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)