mirror of
https://github.com/xemu-project/xemu.git
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PowerPC system emulation (Jocelyn Mayer) - modified patch to use new TLB api
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@528 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
efe160c502
commit
9a64fbe4d8
413
target-ppc/cpu.h
413
target-ppc/cpu.h
@ -25,6 +25,8 @@
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#include "cpu-defs.h"
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//#define USE_OPEN_FIRMWARE
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/*** Sign extend constants ***/
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/* 8 to 32 bits */
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static inline int32_t s_ext8 (uint8_t value)
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@ -54,56 +56,28 @@ static inline int32_t s_ext24 (uint32_t value)
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#include "config.h"
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#include <setjmp.h>
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/* Floting point status and control register */
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#define FPSCR_FX 31
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#define FPSCR_FEX 30
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#define FPSCR_VX 29
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#define FPSCR_OX 28
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#define FPSCR_UX 27
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#define FPSCR_ZX 26
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#define FPSCR_XX 25
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#define FPSCR_VXSNAN 24
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#define FPSCR_VXISI 26
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#define FPSCR_VXIDI 25
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#define FPSCR_VXZDZ 21
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#define FPSCR_VXIMZ 20
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/* Instruction types */
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enum {
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PPC_NONE = 0x0000,
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PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
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PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
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PPC_FLOW = 0x0004, /* CPU has flow control instructions */
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PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
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PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
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PPC_CACHE = 0x0020, /* CPU has cache control instructions */
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PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
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PPC_EXTERN = 0x0080, /* CPU has external control instructions */
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PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
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PPC_CACHE_OPT= 0x0200,
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PPC_FLOAT_OPT= 0x0400,
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PPC_MEM_OPT = 0x0800,
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};
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#define FPSCR_VXVC 18
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#define FPSCR_FR 17
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#define FPSCR_FI 16
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#define FPSCR_FPRF 11
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#define FPSCR_VXSOFT 9
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#define FPSCR_VXSQRT 8
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#define FPSCR_VXCVI 7
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#define FPSCR_OE 6
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#define FPSCR_UE 5
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#define FPSCR_ZE 4
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#define FPSCR_XE 3
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#define FPSCR_NI 2
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#define FPSCR_RN 0
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#define fpscr_fx env->fpscr[FPSCR_FX]
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#define fpscr_fex env->fpscr[FPSCR_FEX]
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#define fpscr_vx env->fpscr[FPSCR_VX]
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#define fpscr_ox env->fpscr[FPSCR_OX]
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#define fpscr_ux env->fpscr[FPSCR_UX]
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#define fpscr_zx env->fpscr[FPSCR_ZX]
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#define fpscr_xx env->fpscr[FPSCR_XX]
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#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN]
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#define fpscr_vxisi env->fpscr[FPSCR_VXISI]
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#define fpscr_vxidi env->fpscr[FPSCR_VXIDI]
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#define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ]
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#define fpscr_vximz env->fpscr[FPSCR_VXIMZ]
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#define fpscr_fr env->fpscr[FPSCR_FR]
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#define fpscr_fi env->fpscr[FPSCR_FI]
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#define fpscr_fprf env->fpscr[FPSCR_FPRF]
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#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT]
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#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT]
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#define fpscr_oe env->fpscr[FPSCR_OE]
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#define fpscr_ue env->fpscr[FPSCR_UE]
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#define fpscr_ze env->fpscr[FPSCR_ZE]
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#define fpscr_xe env->fpscr[FPSCR_XE]
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#define fpscr_ni env->fpscr[FPSCR_NI]
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#define fpscr_rn env->fpscr[FPSCR_RN]
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#define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
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/* PPC 740/745/750/755 (aka G3) has external access instructions */
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#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
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/* Supervisor mode registers */
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/* Machine state register */
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@ -139,26 +113,16 @@ static inline int32_t s_ext24 (uint32_t value)
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#define msr_le env->msr[MSR_LE]
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/* Segment registers */
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typedef struct ppc_sr_t {
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uint32_t t:1;
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uint32_t ks:1;
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uint32_t kp:1;
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uint32_t n:1;
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uint32_t res:4;
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uint32_t vsid:24;
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} ppc_sr_t;
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typedef struct CPUPPCState {
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/* general purpose registers */
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uint32_t gpr[32];
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/* floating point registers */
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double fpr[32];
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/* segment registers */
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ppc_sr_t sr[16];
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/* special purpose registers */
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uint32_t spr[1024];
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uint32_t sdr1;
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uint32_t sr[16];
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/* XER */
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uint8_t xer[32];
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uint8_t xer[4];
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/* Reservation address */
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uint32_t reserve;
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/* machine state register */
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@ -166,11 +130,20 @@ typedef struct CPUPPCState {
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/* condition register */
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uint8_t crf[8];
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/* floating point status and control register */
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uint8_t fpscr[32];
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uint8_t fpscr[8];
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uint32_t nip;
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/* CPU exception code */
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uint32_t exception;
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/* special purpose registers */
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uint32_t lr;
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uint32_t ctr;
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/* Time base */
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uint32_t tb[2];
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/* decrementer */
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uint32_t decr;
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/* BATs */
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uint32_t DBAT[2][8];
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uint32_t IBAT[2][8];
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/* all others */
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uint32_t spr[1024];
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/* qemu dedicated */
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/* temporary float registers */
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double ft0;
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@ -180,9 +153,14 @@ typedef struct CPUPPCState {
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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uint32_t exceptions; /* exception queue */
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uint32_t errors[16];
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int user_mode_only; /* user mode only simulation */
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struct TranslationBlock *current_tb; /* currently executing TB */
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/* soft mmu support */
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/* 0 = kernel, 1 = user */
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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/* user data */
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void *opaque;
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} CPUPPCState;
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@ -198,107 +176,99 @@ int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
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void *puc);
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void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
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void cpu_loop_exit(void);
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void dump_stack (CPUPPCState *env);
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uint32_t _load_xer (void);
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void _store_xer (uint32_t value);
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uint32_t _load_msr (void);
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void _store_msr (uint32_t value);
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void do_interrupt (CPUPPCState *env);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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#define ugpr(n) (env->gpr[n])
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#define fpr(n) (env->fpr[n])
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#define fprd(n) (env->fpr[n])
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#define fprs(n) ((float)env->fpr[n])
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#define fpru(n) ((uint32_t)env->fpr[n])
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#define fpri(n) ((int32_t)env->fpr[n])
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#define SPR_ENCODE(sprn) \
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(((sprn) >> 5) | (((sprn) & 0x1F) << 5))
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/* User mode SPR */
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#define spr(n) env->spr[n]
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//#define XER spr[1]
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#define XER env->xer
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#define XER_SO 31
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#define XER_OV 30
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#define XER_CA 29
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#define XER_BC 0
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#define xer_so env->xer[XER_SO]
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#define xer_ov env->xer[XER_OV]
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#define xer_ca env->xer[XER_CA]
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#define xer_bc env->xer[XER_BC]
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#define xer_so env->xer[3]
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#define xer_ov env->xer[2]
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#define xer_ca env->xer[1]
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#define xer_bc env->xer[0]
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#define LR spr[SPR_ENCODE(8)]
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#define CTR spr[SPR_ENCODE(9)]
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#define XER SPR_ENCODE(1)
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#define LR SPR_ENCODE(8)
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#define CTR SPR_ENCODE(9)
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/* VEA mode SPR */
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#define V_TBL spr[SPR_ENCODE(268)]
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#define V_TBU spr[SPR_ENCODE(269)]
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#define V_TBL SPR_ENCODE(268)
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#define V_TBU SPR_ENCODE(269)
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/* supervisor mode SPR */
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#define DSISR spr[SPR_ENCODE(18)]
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#define DAR spr[SPR_ENCODE(19)]
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#define DEC spr[SPR_ENCODE(22)]
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#define SDR1 spr[SPR_ENCODE(25)]
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typedef struct ppc_sdr1_t {
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uint32_t htaborg:16;
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uint32_t res:7;
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uint32_t htabmask:9;
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} ppc_sdr1_t;
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#define SRR0 spr[SPR_ENCODE(26)]
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#define SRR0_MASK 0xFFFFFFFC
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#define SRR1 spr[SPR_ENCODE(27)]
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#define SPRG0 spr[SPR_ENCODE(272)]
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#define SPRG1 spr[SPR_ENCODE(273)]
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#define SPRG2 spr[SPR_ENCODE(274)]
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#define SPRG3 spr[SPR_ENCODE(275)]
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#define EAR spr[SPR_ENCODE(282)]
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typedef struct ppc_ear_t {
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uint32_t e:1;
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uint32_t res:25;
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uint32_t rid:6;
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} ppc_ear_t;
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#define TBL spr[SPR_ENCODE(284)]
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#define TBU spr[SPR_ENCODE(285)]
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#define PVR spr[SPR_ENCODE(287)]
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typedef struct ppc_pvr_t {
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uint32_t version:16;
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uint32_t revision:16;
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} ppc_pvr_t;
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#define IBAT0U spr[SPR_ENCODE(528)]
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#define IBAT0L spr[SPR_ENCODE(529)]
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#define IBAT1U spr[SPR_ENCODE(530)]
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#define IBAT1L spr[SPR_ENCODE(531)]
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#define IBAT2U spr[SPR_ENCODE(532)]
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#define IBAT2L spr[SPR_ENCODE(533)]
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#define IBAT3U spr[SPR_ENCODE(534)]
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#define IBAT3L spr[SPR_ENCODE(535)]
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#define DBAT0U spr[SPR_ENCODE(536)]
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#define DBAT0L spr[SPR_ENCODE(537)]
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#define DBAT1U spr[SPR_ENCODE(538)]
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#define DBAT1L spr[SPR_ENCODE(539)]
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#define DBAT2U spr[SPR_ENCODE(540)]
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#define DBAT2L spr[SPR_ENCODE(541)]
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#define DBAT3U spr[SPR_ENCODE(542)]
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#define DBAT3L spr[SPR_ENCODE(543)]
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typedef struct ppc_ubat_t {
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uint32_t bepi:15;
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uint32_t res:4;
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uint32_t bl:11;
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uint32_t vs:1;
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uint32_t vp:1;
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} ppc_ubat_t;
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typedef struct ppc_lbat_t {
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uint32_t brpn:15;
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uint32_t res0:10;
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uint32_t w:1;
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uint32_t i:1;
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uint32_t m:1;
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uint32_t g:1;
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uint32_t res1:1;
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uint32_t pp:2;
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} ppc_lbat_t;
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#define DABR spr[SPR_ENCODE(1013)]
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#define DSISR SPR_ENCODE(18)
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#define DAR SPR_ENCODE(19)
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#define DECR SPR_ENCODE(22)
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#define SDR1 SPR_ENCODE(25)
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#define SRR0 SPR_ENCODE(26)
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#define SRR1 SPR_ENCODE(27)
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#define SPRG0 SPR_ENCODE(272)
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#define SPRG1 SPR_ENCODE(273)
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#define SPRG2 SPR_ENCODE(274)
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#define SPRG3 SPR_ENCODE(275)
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#define SPRG4 SPR_ENCODE(276)
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#define SPRG5 SPR_ENCODE(277)
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#define SPRG6 SPR_ENCODE(278)
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#define SPRG7 SPR_ENCODE(279)
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#define ASR SPR_ENCODE(280)
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#define EAR SPR_ENCODE(282)
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#define O_TBL SPR_ENCODE(284)
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#define O_TBU SPR_ENCODE(285)
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#define PVR SPR_ENCODE(287)
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#define IBAT0U SPR_ENCODE(528)
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#define IBAT0L SPR_ENCODE(529)
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#define IBAT1U SPR_ENCODE(530)
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#define IBAT1L SPR_ENCODE(531)
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#define IBAT2U SPR_ENCODE(532)
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#define IBAT2L SPR_ENCODE(533)
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#define IBAT3U SPR_ENCODE(534)
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#define IBAT3L SPR_ENCODE(535)
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#define DBAT0U SPR_ENCODE(536)
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#define DBAT0L SPR_ENCODE(537)
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#define DBAT1U SPR_ENCODE(538)
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#define DBAT1L SPR_ENCODE(539)
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#define DBAT2U SPR_ENCODE(540)
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#define DBAT2L SPR_ENCODE(541)
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#define DBAT3U SPR_ENCODE(542)
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#define DBAT3L SPR_ENCODE(543)
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#define IBAT4U SPR_ENCODE(560)
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#define IBAT4L SPR_ENCODE(561)
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#define IBAT5U SPR_ENCODE(562)
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#define IBAT5L SPR_ENCODE(563)
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#define IBAT6U SPR_ENCODE(564)
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#define IBAT6L SPR_ENCODE(565)
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#define IBAT7U SPR_ENCODE(566)
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#define IBAT7L SPR_ENCODE(567)
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#define DBAT4U SPR_ENCODE(568)
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#define DBAT4L SPR_ENCODE(569)
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#define DBAT5U SPR_ENCODE(570)
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#define DBAT5L SPR_ENCODE(571)
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#define DBAT6U SPR_ENCODE(572)
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#define DBAT6L SPR_ENCODE(573)
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#define DBAT7U SPR_ENCODE(574)
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#define DBAT7L SPR_ENCODE(575)
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#define DABR SPR_ENCODE(1013)
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#define DABR_MASK 0xFFFFFFF8
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typedef struct ppc_dabr_t {
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uint32_t dab:29;
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uint32_t bt:1;
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uint32_t dw:1;
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uint32_t dr:1;
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} ppc_dabr_t;
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#define FPECR spr[SPR_ENCODE(1022)]
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#define PIR spr[SPR_ENCODE(1023)]
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#define FPECR SPR_ENCODE(1022)
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#define PIR SPR_ENCODE(1023)
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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@ -307,10 +277,30 @@ CPUPPCState *cpu_ppc_init(void);
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int cpu_ppc_exec(CPUPPCState *s);
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void cpu_ppc_close(CPUPPCState *s);
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void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
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void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
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uint32_t kernel_addr, uint32_t kernel_size,
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uint32_t stack_addr, int boot_device);
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/* Exeptions */
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/* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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EXCP_NONE = 0x00,
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/* 1 bit to define user level / supervisor access */
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ACCESS_USER = 0x00,
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ACCESS_SUPER = 0x01,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */
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ACCESS_INT = 0x20, /* Integer load/store access */
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ACCESS_FLOAT = 0x30, /* floating point load/store access */
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ACCESS_RES = 0x40, /* load/store with reservation */
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ACCESS_EXT = 0x50, /* external access */
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ACCESS_CACHE = 0x60, /* Cache manipulation */
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};
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/*****************************************************************************/
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/* Exceptions */
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enum {
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EXCP_NONE = -1,
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/* PPC hardware exceptions : exception vector / 0x100 */
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EXCP_RESET = 0x01, /* System reset */
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EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
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@ -326,55 +316,80 @@ enum {
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EXCP_SYSCALL = 0x0C, /* System call */
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EXCP_TRACE = 0x0D, /* Trace exception (optional) */
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EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
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#if 0
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/* Exeption subtypes for EXCP_DSI */
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EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */
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EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */
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EXCP_DSI_PROT = 0x10303, /* Memory protection violation */
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EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */
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EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */
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/* Exeption subtypes for EXCP_ISI */
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EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */
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EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */
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EXCP_ISI_PROT = 0x10403, /* Memory protection violation */
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EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */
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/* Exeption subtypes for EXCP_ALIGN */
|
||||
EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */
|
||||
EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */
|
||||
EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */
|
||||
EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */
|
||||
EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */
|
||||
EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */
|
||||
/* Exeption subtypes for EXCP_PROGRAM */
|
||||
/* FP exceptions */
|
||||
EXCP_FP_OX = 0x10701, /* FP overflow */
|
||||
EXCP_FP_UX = 0x10702, /* FP underflow */
|
||||
EXCP_FP_ZX = 0x10703, /* FP divide by zero */
|
||||
EXCP_FP_XX = 0x10704, /* FP inexact */
|
||||
EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */
|
||||
EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */
|
||||
EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */
|
||||
EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */
|
||||
EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */
|
||||
EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */
|
||||
EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */
|
||||
EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */
|
||||
EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */
|
||||
/* Invalid instruction */
|
||||
EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */
|
||||
EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */
|
||||
EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */
|
||||
EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */
|
||||
#endif
|
||||
EXCP_INVAL = 0x70, /* Invalid instruction */
|
||||
/* Privileged instruction */
|
||||
EXCP_PRIV = 0x71, /* Privileged instruction */
|
||||
/* Trap */
|
||||
EXCP_TRAP = 0x72, /* Trap */
|
||||
/* MPC740/745/750 & IBM 750 */
|
||||
EXCP_PERF = 0x0F, /* Performance monitor */
|
||||
EXCP_IABR = 0x13, /* Instruction address breakpoint */
|
||||
EXCP_SMI = 0x14, /* System management interrupt */
|
||||
EXCP_THRM = 0x15, /* Thermal management interrupt */
|
||||
/* MPC755 */
|
||||
EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
|
||||
EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
|
||||
EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
|
||||
EXCP_PPC_MAX = 0x16,
|
||||
/* Qemu exception */
|
||||
EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
|
||||
EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
|
||||
/* Special cases where we want to stop translation */
|
||||
EXCP_MTMSR = 0x103, /* mtmsr instruction: */
|
||||
/* may change privilege level */
|
||||
EXCP_BRANCH = 0x104, /* branch instruction */
|
||||
EXCP_MTMSR = 0x104, /* mtmsr instruction: */
|
||||
/* may change privilege level */
|
||||
EXCP_BRANCH = 0x108, /* branch instruction */
|
||||
EXCP_RFI = 0x10C, /* return from interrupt */
|
||||
EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
|
||||
};
|
||||
/* Error codes */
|
||||
enum {
|
||||
/* Exception subtypes for EXCP_DSI */
|
||||
EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
|
||||
EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
|
||||
EXCP_DSI_PROT = 0x03, /* Memory protection violation */
|
||||
EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
|
||||
EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
|
||||
/* flags for EXCP_DSI */
|
||||
EXCP_DSI_DIRECT = 0x10,
|
||||
EXCP_DSI_STORE = 0x20,
|
||||
EXCP_ECXW = 0x40,
|
||||
/* Exception subtypes for EXCP_ISI */
|
||||
EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
|
||||
EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
|
||||
EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
|
||||
EXCP_ISI_PROT = 0x04, /* Memory protection violation */
|
||||
/* Exception subtypes for EXCP_ALIGN */
|
||||
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
|
||||
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
|
||||
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
|
||||
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
|
||||
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
|
||||
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
|
||||
/* Exception subtypes for EXCP_PROGRAM */
|
||||
/* FP exceptions */
|
||||
EXCP_FP = 0x10,
|
||||
EXCP_FP_OX = 0x01, /* FP overflow */
|
||||
EXCP_FP_UX = 0x02, /* FP underflow */
|
||||
EXCP_FP_ZX = 0x03, /* FP divide by zero */
|
||||
EXCP_FP_XX = 0x04, /* FP inexact */
|
||||
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
|
||||
EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
|
||||
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
|
||||
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
|
||||
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
|
||||
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
|
||||
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
|
||||
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
|
||||
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
|
||||
/* Invalid instruction */
|
||||
EXCP_INVAL = 0x20,
|
||||
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
|
||||
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
|
||||
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
|
||||
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
|
||||
/* Privileged instruction */
|
||||
EXCP_PRIV = 0x30,
|
||||
EXCP_PRIV_OPC = 0x01,
|
||||
EXCP_PRIV_REG = 0x02,
|
||||
/* Trap */
|
||||
EXCP_TRAP = 0x40,
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
#endif /* !defined (__CPU_PPC_H__) */
|
||||
|
||||
@ -41,126 +41,119 @@ register uint32_t T2 asm(AREG3);
|
||||
#include "cpu.h"
|
||||
#include "exec-all.h"
|
||||
|
||||
static inline uint8_t ld8 (uint32_t EA)
|
||||
{
|
||||
return *((uint8_t *)EA);
|
||||
}
|
||||
|
||||
static inline uint16_t ld16 (uint32_t EA)
|
||||
{
|
||||
return __be16_to_cpu(*((uint16_t *)EA));
|
||||
}
|
||||
|
||||
static inline uint16_t ld16r (uint32_t EA)
|
||||
{
|
||||
return __le16_to_cpu(*((uint16_t *)EA));
|
||||
}
|
||||
|
||||
static inline uint32_t ld32 (uint32_t EA)
|
||||
{
|
||||
return __be32_to_cpu(*((uint32_t *)EA));
|
||||
}
|
||||
|
||||
static inline uint32_t ld32r (uint32_t EA)
|
||||
{
|
||||
return __le32_to_cpu(*((uint32_t *)EA));
|
||||
}
|
||||
|
||||
static inline uint64_t ld64 (uint32_t EA)
|
||||
{
|
||||
return __be64_to_cpu(*((uint64_t *)EA));
|
||||
}
|
||||
|
||||
static inline uint64_t ld64r (uint32_t EA)
|
||||
{
|
||||
return __le64_to_cpu(*((uint64_t *)EA));
|
||||
}
|
||||
|
||||
static inline void st8 (uint32_t EA, uint8_t data)
|
||||
{
|
||||
*((uint8_t *)EA) = data;
|
||||
}
|
||||
|
||||
static inline void st16 (uint32_t EA, uint16_t data)
|
||||
{
|
||||
*((uint16_t *)EA) = __cpu_to_be16(data);
|
||||
}
|
||||
|
||||
static inline void st16r (uint32_t EA, uint16_t data)
|
||||
{
|
||||
*((uint16_t *)EA) = __cpu_to_le16(data);
|
||||
}
|
||||
|
||||
static inline void st32 (uint32_t EA, uint32_t data)
|
||||
{
|
||||
*((uint32_t *)EA) = __cpu_to_be32(data);
|
||||
}
|
||||
|
||||
static inline void st32r (uint32_t EA, uint32_t data)
|
||||
{
|
||||
*((uint32_t *)EA) = __cpu_to_le32(data);
|
||||
}
|
||||
|
||||
static inline void st64 (uint32_t EA, uint64_t data)
|
||||
{
|
||||
*((uint64_t *)EA) = __cpu_to_be64(data);
|
||||
}
|
||||
|
||||
static inline void st64r (uint32_t EA, uint64_t data)
|
||||
{
|
||||
*((uint64_t *)EA) = __cpu_to_le64(data);
|
||||
}
|
||||
|
||||
static inline void set_CRn(int n, uint8_t value)
|
||||
{
|
||||
env->crf[n] = value;
|
||||
}
|
||||
|
||||
static inline void set_carry (void)
|
||||
{
|
||||
xer_ca = 1;
|
||||
}
|
||||
|
||||
static inline void reset_carry (void)
|
||||
{
|
||||
xer_ca = 0;
|
||||
}
|
||||
|
||||
static inline void set_overflow (void)
|
||||
{
|
||||
xer_so = 1;
|
||||
xer_ov = 1;
|
||||
}
|
||||
|
||||
static inline void reset_overflow (void)
|
||||
{
|
||||
xer_ov = 0;
|
||||
}
|
||||
|
||||
static inline uint32_t rotl (uint32_t i, int n)
|
||||
{
|
||||
return ((i << n) | (i >> (32 - n)));
|
||||
}
|
||||
|
||||
void raise_exception (int exception_index);
|
||||
void raise_exception_err (int exception_index, int error_code);
|
||||
/* XXX: move that to a generic header */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
uint32_t do_load_cr (void);
|
||||
void do_store_cr (uint32_t crn, uint32_t value);
|
||||
uint32_t do_load_xer (void);
|
||||
void do_store_xer (uint32_t value);
|
||||
uint32_t do_load_msr (void);
|
||||
void do_store_msr (uint32_t msr_value);
|
||||
#define ldul_user ldl_user
|
||||
#define ldul_kernel ldl_kernel
|
||||
|
||||
#define ACCESS_TYPE 0
|
||||
#define MEMSUFFIX _kernel
|
||||
#define DATA_SIZE 1
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "softmmu_header.h"
|
||||
#undef ACCESS_TYPE
|
||||
#undef MEMSUFFIX
|
||||
|
||||
#define ACCESS_TYPE 1
|
||||
#define MEMSUFFIX _user
|
||||
#define DATA_SIZE 1
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "softmmu_header.h"
|
||||
#undef ACCESS_TYPE
|
||||
#undef MEMSUFFIX
|
||||
|
||||
/* these access are slower, they must be as rare as possible */
|
||||
#define ACCESS_TYPE 2
|
||||
#define MEMSUFFIX _data
|
||||
#define DATA_SIZE 1
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 2
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 4
|
||||
#include "softmmu_header.h"
|
||||
|
||||
#define DATA_SIZE 8
|
||||
#include "softmmu_header.h"
|
||||
#undef ACCESS_TYPE
|
||||
#undef MEMSUFFIX
|
||||
|
||||
#define ldub(p) ldub_data(p)
|
||||
#define ldsb(p) ldsb_data(p)
|
||||
#define lduw(p) lduw_data(p)
|
||||
#define ldsw(p) ldsw_data(p)
|
||||
#define ldl(p) ldl_data(p)
|
||||
#define ldq(p) ldq_data(p)
|
||||
|
||||
#define stb(p, v) stb_data(p, v)
|
||||
#define stw(p, v) stw_data(p, v)
|
||||
#define stl(p, v) stl_data(p, v)
|
||||
#define stq(p, v) stq_data(p, v)
|
||||
|
||||
#endif /* !defined(CONFIG_USER_ONLY) */
|
||||
|
||||
int check_exception_state (CPUState *env);
|
||||
|
||||
void do_queue_exception_err (uint32_t exception, int error_code);
|
||||
void do_queue_exception (uint32_t exception);
|
||||
void do_process_exceptions (void);
|
||||
void do_check_exception_state (void);
|
||||
|
||||
void do_load_cr (void);
|
||||
void do_store_cr (uint32_t mask);
|
||||
void do_load_xer (void);
|
||||
void do_store_xer (void);
|
||||
void do_load_msr (void);
|
||||
void do_store_msr (void);
|
||||
void do_load_fpscr (void);
|
||||
void do_store_fpscr (uint32_t mask);
|
||||
|
||||
int32_t do_sraw(int32_t Ta, uint32_t Tb);
|
||||
void do_lmw (int reg, uint32_t src);
|
||||
void do_stmw (int reg, uint32_t dest);
|
||||
void do_lsw (uint32_t reg, int count, uint32_t src);
|
||||
void do_stsw (uint32_t reg, int count, uint32_t dest);
|
||||
void do_sraw(void);
|
||||
|
||||
void do_fctiw (void);
|
||||
void do_fctiwz (void);
|
||||
void do_fsqrt (void);
|
||||
void do_fsqrts (void);
|
||||
void do_fres (void);
|
||||
void do_fsqrte (void);
|
||||
void do_fsel (void);
|
||||
void do_fcmpu (void);
|
||||
void do_fcmpo (void);
|
||||
void do_fabs (void);
|
||||
void do_fnabs (void);
|
||||
|
||||
void do_dcbz (void);
|
||||
void do_icbi (void);
|
||||
void do_tlbia (void);
|
||||
void do_tlbie (void);
|
||||
|
||||
void dump_rfi (void);
|
||||
void dump_store_sr (int srnum);
|
||||
void dump_store_ibat (int ul, int nr);
|
||||
void dump_store_dbat (int ul, int nr);
|
||||
void dump_store_tb (int ul);
|
||||
void dump_update_tb(uint32_t param);
|
||||
|
||||
#endif /* !defined (__PPC_H__) */
|
||||
|
||||
1050
target-ppc/helper.c
1050
target-ppc/helper.c
File diff suppressed because it is too large
Load Diff
935
target-ppc/hw.c
Normal file
935
target-ppc/hw.c
Normal file
@ -0,0 +1,935 @@
|
||||
/*
|
||||
* Hardware simulation for PPC target.
|
||||
* For now, this is only a 'minimal' collection of hacks needed to boot Linux.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
#include <ctype.h>
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <inttypes.h>
|
||||
#include <unistd.h>
|
||||
#include <time.h>
|
||||
|
||||
#include "cpu.h"
|
||||
#include "vl.h"
|
||||
|
||||
//#define HARD_DEBUG_PPC_IO
|
||||
#define DEBUG_PPC_IO
|
||||
|
||||
extern int loglevel;
|
||||
extern FILE *logfile;
|
||||
|
||||
#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
|
||||
#define DEBUG_PPC_IO
|
||||
#endif
|
||||
|
||||
#if defined (HARD_DEBUG_PPC_IO)
|
||||
#define PPC_IO_DPRINTF(fmt, args...) \
|
||||
do { \
|
||||
if (loglevel > 0) { \
|
||||
fprintf(logfile, "%s: " fmt, __func__ , ##args); \
|
||||
} else { \
|
||||
printf("%s : " fmt, __func__ , ##args); \
|
||||
} \
|
||||
} while (0)
|
||||
#elif defined (DEBUG_PPC_IO)
|
||||
#define PPC_IO_DPRINTF(fmt, args...) \
|
||||
do { \
|
||||
if (loglevel > 0) { \
|
||||
fprintf(logfile, "%s: " fmt, __func__ , ##args); \
|
||||
} \
|
||||
} while (0)
|
||||
#else
|
||||
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#if defined (USE_OPEN_FIRMWARE)
|
||||
#include "of.h"
|
||||
#else
|
||||
#define NVRAM_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
/* IO ports emulation */
|
||||
#define PPC_IO_BASE 0x80000000
|
||||
|
||||
static void PPC_io_writeb (uint32_t addr, uint32_t value)
|
||||
{
|
||||
/* Don't polute serial port output */
|
||||
if ((addr < 0x800003F0 || addr > 0x80000400) &&
|
||||
(addr < 0x80000074 || addr > 0x80000077) &&
|
||||
(addr < 0x80000020 || addr > 0x80000021) &&
|
||||
(addr < 0x800000a0 || addr > 0x800000a1) &&
|
||||
(addr < 0x800001f0 || addr > 0x800001f7) &&
|
||||
(addr < 0x80000170 || addr > 0x80000177)) {
|
||||
PPC_IO_DPRINTF("0x%08x => 0x%02x\n", addr - PPC_IO_BASE, value);
|
||||
}
|
||||
cpu_outb(NULL, addr - PPC_IO_BASE, value);
|
||||
}
|
||||
|
||||
static uint32_t PPC_io_readb (uint32_t addr)
|
||||
{
|
||||
uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
|
||||
|
||||
if ((addr < 0x800003F0 || addr > 0x80000400) &&
|
||||
(addr < 0x80000074 || addr > 0x80000077) &&
|
||||
(addr < 0x80000020 || addr > 0x80000021) &&
|
||||
(addr < 0x800000a0 || addr > 0x800000a1) &&
|
||||
(addr < 0x800001f0 || addr > 0x800001f7) &&
|
||||
(addr < 0x80000170 || addr > 0x80000177) &&
|
||||
(addr < 0x8000060 || addr > 0x8000064)) {
|
||||
// PPC_IO_DPRINTF("0x%08x <= 0x%02x\n", addr - PPC_IO_BASE, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void PPC_io_writew (uint32_t addr, uint32_t value)
|
||||
{
|
||||
if ((addr < 0x800001f0 || addr > 0x800001f7) &&
|
||||
(addr < 0x80000170 || addr > 0x80000177)) {
|
||||
PPC_IO_DPRINTF("0x%08x => 0x%04x\n", addr - PPC_IO_BASE, value);
|
||||
}
|
||||
cpu_outw(NULL, addr - PPC_IO_BASE, value);
|
||||
}
|
||||
|
||||
static uint32_t PPC_io_readw (uint32_t addr)
|
||||
{
|
||||
uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
|
||||
|
||||
if ((addr < 0x800001f0 || addr > 0x800001f7) &&
|
||||
(addr < 0x80000170 || addr > 0x80000177)) {
|
||||
PPC_IO_DPRINTF("0x%08x <= 0x%04x\n", addr - PPC_IO_BASE, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void PPC_io_writel (uint32_t addr, uint32_t value)
|
||||
{
|
||||
PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
|
||||
cpu_outl(NULL, addr - PPC_IO_BASE, value);
|
||||
}
|
||||
|
||||
static uint32_t PPC_io_readl (uint32_t addr)
|
||||
{
|
||||
uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
|
||||
|
||||
PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static CPUWriteMemoryFunc *PPC_io_write[] = {
|
||||
&PPC_io_writeb,
|
||||
&PPC_io_writew,
|
||||
&PPC_io_writel,
|
||||
};
|
||||
|
||||
static CPUReadMemoryFunc *PPC_io_read[] = {
|
||||
&PPC_io_readb,
|
||||
&PPC_io_readw,
|
||||
&PPC_io_readl,
|
||||
};
|
||||
|
||||
uint32_t pic_intack_read(CPUState *env);
|
||||
|
||||
/* Read-only register (?) */
|
||||
static void _PPC_ioB_write (uint32_t addr, uint32_t value)
|
||||
{
|
||||
PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr, value);
|
||||
}
|
||||
|
||||
static uint32_t _PPC_ioB_read (uint32_t addr)
|
||||
{
|
||||
uint32_t retval = 0;
|
||||
|
||||
if (addr == 0xBFFFFFF0)
|
||||
retval = pic_intack_read(NULL);
|
||||
PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static CPUWriteMemoryFunc *PPC_ioB_write[] = {
|
||||
&_PPC_ioB_write,
|
||||
&_PPC_ioB_write,
|
||||
&_PPC_ioB_write,
|
||||
};
|
||||
|
||||
static CPUReadMemoryFunc *PPC_ioB_read[] = {
|
||||
&_PPC_ioB_read,
|
||||
&_PPC_ioB_read,
|
||||
&_PPC_ioB_read,
|
||||
};
|
||||
|
||||
#if 0
|
||||
static CPUWriteMemoryFunc *PPC_io3_write[] = {
|
||||
&PPC_io3_writeb,
|
||||
&PPC_io3_writew,
|
||||
&PPC_io3_writel,
|
||||
};
|
||||
|
||||
static CPUReadMemoryFunc *PPC_io3_read[] = {
|
||||
&PPC_io3_readb,
|
||||
&PPC_io3_readw,
|
||||
&PPC_io3_readl,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
|
||||
static uint8_t PREP_fake_io[2];
|
||||
static uint8_t NVRAM_lock;
|
||||
|
||||
static void PREP_io_write (CPUState *env, uint32_t addr, uint32_t val)
|
||||
{
|
||||
PREP_fake_io[addr - 0x0398] = val;
|
||||
}
|
||||
|
||||
static uint32_t PREP_io_read (CPUState *env, uint32_t addr)
|
||||
{
|
||||
return PREP_fake_io[addr - 0x0398];
|
||||
}
|
||||
|
||||
static uint8_t syscontrol;
|
||||
|
||||
static void PREP_io_800_writeb (CPUState *env, uint32_t addr, uint32_t val)
|
||||
{
|
||||
switch (addr) {
|
||||
case 0x0092:
|
||||
/* Special port 92 */
|
||||
/* Check soft reset asked */
|
||||
if (val & 0x80) {
|
||||
printf("Soft reset asked... Stop emulation\n");
|
||||
abort();
|
||||
}
|
||||
/* Check LE mode */
|
||||
if (val & 0x40) {
|
||||
printf("Little Endian mode isn't supported (yet ?)\n");
|
||||
abort();
|
||||
}
|
||||
break;
|
||||
case 0x0808:
|
||||
/* Hardfile light register: don't care */
|
||||
break;
|
||||
case 0x0810:
|
||||
/* Password protect 1 register */
|
||||
NVRAM_lock ^= 0x01;
|
||||
break;
|
||||
case 0x0812:
|
||||
/* Password protect 2 register */
|
||||
NVRAM_lock ^= 0x02;
|
||||
break;
|
||||
case 0x0814:
|
||||
/* L2 invalidate register: don't care */
|
||||
break;
|
||||
case 0x081C:
|
||||
/* system control register */
|
||||
syscontrol = val;
|
||||
break;
|
||||
case 0x0850:
|
||||
/* I/O map type register */
|
||||
if (val & 0x80) {
|
||||
printf("No support for non-continuous I/O map mode\n");
|
||||
abort();
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t PREP_io_800_readb (CPUState *env, uint32_t addr)
|
||||
{
|
||||
uint32_t retval = 0xFF;
|
||||
|
||||
switch (addr) {
|
||||
case 0x0092:
|
||||
/* Special port 92 */
|
||||
retval = 0x40;
|
||||
break;
|
||||
case 0x080C:
|
||||
/* Equipment present register:
|
||||
* no L2 cache
|
||||
* no upgrade processor
|
||||
* no cards in PCI slots
|
||||
* SCSI fuse is bad
|
||||
*/
|
||||
retval = 0xFC;
|
||||
break;
|
||||
case 0x0818:
|
||||
/* Keylock */
|
||||
retval = 0x00;
|
||||
break;
|
||||
case 0x081C:
|
||||
/* system control register
|
||||
* 7 - 6 / 1 - 0: L2 cache enable
|
||||
*/
|
||||
retval = syscontrol;
|
||||
break;
|
||||
case 0x0823:
|
||||
/* */
|
||||
retval = 0x03; /* no L2 cache */
|
||||
break;
|
||||
case 0x0850:
|
||||
/* I/O map type register */
|
||||
retval = 0x00;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* M48T59 NVRAM/RTC emulation */
|
||||
static uint8_t NVRAM[NVRAM_SIZE];
|
||||
|
||||
/* RTC */
|
||||
static time_t time_offset;
|
||||
|
||||
time_t get_time (void)
|
||||
{
|
||||
return time(NULL) + time_offset;
|
||||
}
|
||||
|
||||
void set_time_offset (time_t new_time)
|
||||
{
|
||||
time_t now = time(NULL);
|
||||
|
||||
time_offset = new_time - now;
|
||||
}
|
||||
|
||||
static void NVRAM_init (void)
|
||||
{
|
||||
/* NVRAM header */
|
||||
/* 0x00: NVRAM size in kB */
|
||||
NVRAM[0x00] = (NVRAM_SIZE >> 12) & 0xFF;
|
||||
NVRAM[0x01] = (NVRAM_SIZE >> 10) & 0xFF;
|
||||
/* 0x02: NVRAM version */
|
||||
NVRAM[0x02] = 0x01;
|
||||
/* 0x03: NVRAM revision */
|
||||
NVRAM[0x03] = 0x00;
|
||||
/* 0x04: checksum 0 => OS area */
|
||||
/* 0x06: checksum of config area */
|
||||
/* 0x08: last OS */
|
||||
NVRAM[0x08] = 0x00; /* Unknown */
|
||||
/* 0x09: endian */
|
||||
NVRAM[0x09] = 'B';
|
||||
/* 0x0B: PM mode */
|
||||
NVRAM[0x0B] = 0x00;
|
||||
/* Restart block description record */
|
||||
/* 0x0C: restart block version */
|
||||
NVRAM[0x0C] = 0x00;
|
||||
NVRAM[0x0D] = 0x01;
|
||||
/* 0x0E: restart block revision */
|
||||
NVRAM[0x0E] = 0x00;
|
||||
NVRAM[0x0F] = 0x00;
|
||||
/* 0x1C: checksum of restart block */
|
||||
/* 0x20: restart address */
|
||||
NVRAM[0x20] = 0x00;
|
||||
NVRAM[0x21] = 0x00;
|
||||
NVRAM[0x22] = 0x00;
|
||||
NVRAM[0x23] = 0x00;
|
||||
/* 0x24: save area address */
|
||||
NVRAM[0x24] = 0x00;
|
||||
NVRAM[0x25] = 0x00;
|
||||
NVRAM[0x26] = 0x00;
|
||||
NVRAM[0x27] = 0x00;
|
||||
/* 0x28: save area length */
|
||||
NVRAM[0x28] = 0x00;
|
||||
NVRAM[0x29] = 0x00;
|
||||
NVRAM[0x2A] = 0x00;
|
||||
NVRAM[0x2B] = 0x00;
|
||||
/* Security section */
|
||||
/* Set all to zero */
|
||||
/* 0xC4: pointer to global environment area */
|
||||
NVRAM[0xC4] = 0x00;
|
||||
NVRAM[0xC5] = 0x00;
|
||||
NVRAM[0xC6] = 0x01;
|
||||
NVRAM[0xC7] = 0x00;
|
||||
/* 0xC8: size of global environment area */
|
||||
NVRAM[0xC8] = 0x00;
|
||||
NVRAM[0xC9] = 0x00;
|
||||
NVRAM[0xCA] = 0x07;
|
||||
NVRAM[0xCB] = 0x00;
|
||||
/* 0xD4: pointer to configuration area */
|
||||
NVRAM[0xD4] = 0x00;
|
||||
NVRAM[0xD5] = 0x00;
|
||||
NVRAM[0xD6] = 0x08;
|
||||
NVRAM[0xD7] = 0x00;
|
||||
/* 0xD8: size of configuration area */
|
||||
NVRAM[0xD8] = 0x00;
|
||||
NVRAM[0xD9] = 0x00;
|
||||
NVRAM[0xDA] = 0x08;
|
||||
NVRAM[0xDB] = 0x00;
|
||||
/* 0xE8: pointer to OS specific area */
|
||||
NVRAM[0xE8] = 0x00;
|
||||
NVRAM[0xE9] = 0x00;
|
||||
NVRAM[0xEA] = 0x10;
|
||||
NVRAM[0xEB] = 0x00;
|
||||
/* 0xD8: size of OS specific area */
|
||||
NVRAM[0xEC] = 0x00;
|
||||
NVRAM[0xED] = 0x00;
|
||||
NVRAM[0xEE] = 0x0F;
|
||||
NVRAM[0xEF] = 0xF0;
|
||||
/* CRC */
|
||||
/* RTC init */
|
||||
NVRAM[0x1FFC] = 0x50;
|
||||
}
|
||||
|
||||
static uint16_t NVRAM_addr;
|
||||
|
||||
/* Direct access to NVRAM */
|
||||
void NVRAM_write (CPUState *env, uint32_t addr, uint32_t val)
|
||||
{
|
||||
switch (addr) {
|
||||
case 0x1FF0:
|
||||
/* flags register */
|
||||
break;
|
||||
case 0x1FF1:
|
||||
/* unused */
|
||||
break;
|
||||
case 0x1FF2:
|
||||
/* alarm seconds */
|
||||
break;
|
||||
case 0x1FF3:
|
||||
/* alarm minutes */
|
||||
break;
|
||||
case 0x1FF4:
|
||||
/* alarm hours */
|
||||
break;
|
||||
case 0x1FF5:
|
||||
/* alarm date */
|
||||
break;
|
||||
case 0x1FF6:
|
||||
/* interrupts */
|
||||
break;
|
||||
case 0x1FF7:
|
||||
/* watchdog */
|
||||
break;
|
||||
case 0x1FF8:
|
||||
/* control */
|
||||
break;
|
||||
case 0x1FF9:
|
||||
/* seconds (BCD) */
|
||||
break;
|
||||
case 0x1FFA:
|
||||
/* minutes (BCD) */
|
||||
break;
|
||||
case 0x1FFB:
|
||||
/* hours (BCD) */
|
||||
break;
|
||||
case 0x1FFC:
|
||||
/* day of the week / century */
|
||||
NVRAM[0x1FFC] = val & 0x50;
|
||||
break;
|
||||
case 0x1FFD:
|
||||
/* date */
|
||||
break;
|
||||
case 0x1FFE:
|
||||
/* month */
|
||||
break;
|
||||
case 0x1FFF:
|
||||
/* year */
|
||||
break;
|
||||
default:
|
||||
if (addr < NVRAM_SIZE)
|
||||
NVRAM[addr] = val & 0xFF;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t NVRAM_read (CPUState *env, uint32_t addr)
|
||||
{
|
||||
struct tm tm;
|
||||
time_t t;
|
||||
uint32_t retval = 0xFF;
|
||||
|
||||
switch (addr) {
|
||||
case 0x1FF0:
|
||||
/* flags register */
|
||||
break;
|
||||
case 0x1FF1:
|
||||
/* unused */
|
||||
break;
|
||||
case 0x1FF2:
|
||||
/* alarm seconds */
|
||||
break;
|
||||
case 0x1FF3:
|
||||
/* alarm minutes */
|
||||
break;
|
||||
case 0x1FF4:
|
||||
/* alarm hours */
|
||||
break;
|
||||
case 0x1FF5:
|
||||
/* alarm date */
|
||||
break;
|
||||
case 0x1FF6:
|
||||
/* interrupts */
|
||||
break;
|
||||
case 0x1FF7:
|
||||
/* watchdog */
|
||||
break;
|
||||
case 0x1FF8:
|
||||
/* control */
|
||||
break;
|
||||
case 0x1FF9:
|
||||
/* seconds (BCD) */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_sec / 10) << 4) | (tm.tm_sec % 10);
|
||||
// printf("return seconds=%d\n", tm.tm_sec);
|
||||
break;
|
||||
case 0x1FFA:
|
||||
/* minutes (BCD) */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_min / 10) << 4) | (tm.tm_min % 10);
|
||||
break;
|
||||
case 0x1FFB:
|
||||
/* hours (BCD) */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_hour / 10) << 4) | (tm.tm_hour % 10);
|
||||
break;
|
||||
case 0x1FFC:
|
||||
/* day of the week / century */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = (NVRAM[0x1FFC] & 0x50) | tm.tm_wday;
|
||||
break;
|
||||
case 0x1FFD:
|
||||
/* date */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_mday / 10) << 4) | (tm.tm_mday % 10);
|
||||
break;
|
||||
case 0x1FFE:
|
||||
/* month */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_mon / 10) << 4) | (tm.tm_mon % 10);
|
||||
break;
|
||||
case 0x1FFF:
|
||||
/* year */
|
||||
t = get_time();
|
||||
localtime_r(&t, &tm);
|
||||
retval = ((tm.tm_year / 10) << 4) | (tm.tm_year % 10);
|
||||
break;
|
||||
default:
|
||||
if (NVRAM_addr < NVRAM_SIZE)
|
||||
retval = NVRAM[NVRAM_addr];
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* IO access to NVRAM */
|
||||
static void NVRAM_writeb (CPUState *env, uint32_t addr, uint32_t val)
|
||||
{
|
||||
switch (addr) {
|
||||
case 0x74:
|
||||
NVRAM_addr &= ~0x00FF;
|
||||
NVRAM_addr |= val;
|
||||
break;
|
||||
case 0x75:
|
||||
NVRAM_addr &= ~0xFF00;
|
||||
NVRAM_addr |= val << 8;
|
||||
break;
|
||||
case 0x77:
|
||||
NVRAM_write(env, NVRAM_addr, val);
|
||||
NVRAM_addr = 0x0000;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t NVRAM_readb (CPUState *env, uint32_t addr)
|
||||
{
|
||||
if (addr == 0x77)
|
||||
return NVRAM_read(env, NVRAM_addr);
|
||||
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
int load_initrd (const char *filename, uint8_t *addr)
|
||||
{
|
||||
int fd, size;
|
||||
|
||||
printf("Load initrd\n");
|
||||
fd = open(filename, O_RDONLY);
|
||||
if (fd < 0)
|
||||
return -1;
|
||||
size = read(fd, addr, 16 * 1024 * 1024);
|
||||
if (size < 0)
|
||||
goto fail;
|
||||
close(fd);
|
||||
printf("Load initrd: %d\n", size);
|
||||
return size;
|
||||
fail:
|
||||
close(fd);
|
||||
printf("Load initrd failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Quick hack for PPC memory infos... */
|
||||
static void put_long (void *addr, uint32_t l)
|
||||
{
|
||||
char *pos = addr;
|
||||
pos[0] = (l >> 24) & 0xFF;
|
||||
pos[1] = (l >> 16) & 0xFF;
|
||||
pos[2] = (l >> 8) & 0xFF;
|
||||
pos[3] = l & 0xFF;
|
||||
}
|
||||
|
||||
/* bootloader infos are in the form:
|
||||
* uint32_t TAG
|
||||
* uint32_t TAG_size (from TAG to next TAG).
|
||||
* datas
|
||||
* ....
|
||||
*/
|
||||
#if !defined (USE_OPEN_FIRMWARE)
|
||||
static void *set_bootinfo_tag (void *addr, uint32_t tag, uint32_t size,
|
||||
void *data)
|
||||
{
|
||||
char *pos = addr;
|
||||
|
||||
put_long(pos, tag);
|
||||
pos += 4;
|
||||
put_long(pos, size + 8);
|
||||
pos += 4;
|
||||
memcpy(pos, data, size);
|
||||
pos += size;
|
||||
|
||||
return pos;
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef struct boot_dev_t {
|
||||
const unsigned char *name;
|
||||
int major;
|
||||
int minor;
|
||||
} boot_dev_t;
|
||||
|
||||
static boot_dev_t boot_devs[] =
|
||||
{
|
||||
{ "/dev/fd0", 2, 0, },
|
||||
{ "/dev/fd1", 2, 1, },
|
||||
{ "/dev/hda1", 3, 1, },
|
||||
// { "/dev/ide/host0/bus0/target0/lun0/part1", 3, 1, },
|
||||
{ "/dev/hdc", 22, 0, },
|
||||
{ "/dev/ram0 init=/linuxrc", 1, 0, },
|
||||
};
|
||||
|
||||
/* BATU:
|
||||
* BEPI : bloc virtual address
|
||||
* BL : area size bits (128 kB is 0, 256 1, 512 3, ...
|
||||
* Vs/Vp
|
||||
* BATL:
|
||||
* BPRN : bloc real address align on 4MB boundary
|
||||
* WIMG : cache access mode : not used
|
||||
* PP : protection bits
|
||||
*/
|
||||
static void setup_BAT (CPUPPCState *env, int BAT,
|
||||
uint32_t virtual, uint32_t physical,
|
||||
uint32_t size, int Vs, int Vp, int PP)
|
||||
{
|
||||
uint32_t sz_bits, tmp_sz, align, tmp;
|
||||
|
||||
sz_bits = 0;
|
||||
align = 131072;
|
||||
for (tmp_sz = size / 131072; tmp_sz != 1; tmp_sz = tmp_sz >> 1) {
|
||||
sz_bits = (sz_bits << 1) + 1;
|
||||
align = align << 1;
|
||||
}
|
||||
tmp = virtual & ~(align - 1); /* Align virtual area start */
|
||||
tmp |= sz_bits << 2; /* Fix BAT size */
|
||||
tmp |= Vs << 1; /* Supervisor access */
|
||||
tmp |= Vp; /* User access */
|
||||
env->DBAT[0][BAT] = tmp;
|
||||
env->IBAT[0][BAT] = tmp;
|
||||
tmp = physical & ~(align - 1); /* Align physical area start */
|
||||
tmp |= 0; /* Don't care about WIMG */
|
||||
tmp |= PP; /* Protection */
|
||||
env->DBAT[1][BAT] = tmp;
|
||||
env->IBAT[1][BAT] = tmp;
|
||||
printf("Set BATU0 to 0x%08x BATL0 to 0x%08x\n",
|
||||
env->DBAT[0][BAT], env->DBAT[1][BAT]);
|
||||
}
|
||||
|
||||
static void VGA_printf (uint8_t *s)
|
||||
{
|
||||
uint16_t *arg_ptr;
|
||||
unsigned int format_width, i;
|
||||
int in_format;
|
||||
uint16_t arg, digit, nibble;
|
||||
uint8_t c;
|
||||
|
||||
arg_ptr = (uint16_t *)(&s);
|
||||
in_format = 0;
|
||||
format_width = 0;
|
||||
while ((c = *s) != '\0') {
|
||||
if (c == '%') {
|
||||
in_format = 1;
|
||||
format_width = 0;
|
||||
} else if (in_format) {
|
||||
if ((c >= '0') && (c <= '9')) {
|
||||
format_width = (format_width * 10) + (c - '0');
|
||||
} else if (c == 'x') {
|
||||
arg_ptr++; // increment to next arg
|
||||
arg = *arg_ptr;
|
||||
if (format_width == 0)
|
||||
format_width = 4;
|
||||
digit = format_width - 1;
|
||||
for (i = 0; i < format_width; i++) {
|
||||
nibble = (arg >> (4 * digit)) & 0x000f;
|
||||
if (nibble <= 9)
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0');
|
||||
else
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A');
|
||||
digit--;
|
||||
}
|
||||
in_format = 0;
|
||||
}
|
||||
//else if (c == 'd') {
|
||||
// in_format = 0;
|
||||
// }
|
||||
} else {
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x500, c);
|
||||
}
|
||||
s++;
|
||||
}
|
||||
}
|
||||
|
||||
static void VGA_init (void)
|
||||
{
|
||||
/* Basic VGA init, inspired by plex86 VGAbios */
|
||||
printf("Init VGA...\n");
|
||||
/* switch to color mode and enable CPU access 480 lines */
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3);
|
||||
/* more than 64k 3C4/04 */
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04);
|
||||
PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02);
|
||||
VGA_printf("PPC VGA BIOS...\n");
|
||||
}
|
||||
|
||||
void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
|
||||
uint32_t kernel_addr, uint32_t kernel_size,
|
||||
uint32_t stack_addr, int boot_device)
|
||||
{
|
||||
char *p;
|
||||
#if !defined (USE_OPEN_FIRMWARE)
|
||||
char *tmp;
|
||||
uint32_t tmpi[2];
|
||||
#endif
|
||||
int PPC_io_memory;
|
||||
|
||||
#if defined (USE_OPEN_FIRMWARE)
|
||||
setup_memory(env, mem_size);
|
||||
#endif
|
||||
/* Register 64 kB of IO space */
|
||||
PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
|
||||
cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
|
||||
/* Register fake IO ports for PREP */
|
||||
register_ioport_read(0x398, 2, PREP_io_read, 1);
|
||||
register_ioport_write(0x398, 2, PREP_io_write, 1);
|
||||
/* System control ports */
|
||||
register_ioport_write(0x0092, 0x1, PREP_io_800_writeb, 1);
|
||||
register_ioport_read(0x0800, 0x52, PREP_io_800_readb, 1);
|
||||
register_ioport_write(0x0800, 0x52, PREP_io_800_writeb, 1);
|
||||
/* PCI intack location */
|
||||
PPC_io_memory = cpu_register_io_memory(0, PPC_ioB_read, PPC_ioB_write);
|
||||
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
|
||||
/* NVRAM ports */
|
||||
NVRAM_init();
|
||||
register_ioport_read(0x0074, 0x04, NVRAM_readb, 1);
|
||||
register_ioport_write(0x0074, 0x04, NVRAM_writeb, 1);
|
||||
|
||||
/* Fake bootloader */
|
||||
env->nip = kernel_addr + (3 * sizeof(uint32_t));
|
||||
/* Set up msr according to PREP specification */
|
||||
msr_ee = 0;
|
||||
msr_fp = 1;
|
||||
msr_pr = 0; /* Start in supervisor mode */
|
||||
msr_me = 1;
|
||||
msr_fe0 = msr_fe1 = 0;
|
||||
msr_ip = 0;
|
||||
msr_ir = msr_dr = 1;
|
||||
// msr_sf = 0;
|
||||
msr_le = msr_ile = 0;
|
||||
env->gpr[1] = stack_addr; /* Let's have a stack */
|
||||
env->gpr[2] = 0;
|
||||
env->gpr[8] = kernel_addr;
|
||||
/* There is a bug in 2.4 kernels:
|
||||
* if a decrementer exception is pending when it enables msr_ee,
|
||||
* it's not ready to handle it...
|
||||
*/
|
||||
env->decr = 0xFFFFFFFF;
|
||||
p = (void *)(phys_ram_base + kernel_addr);
|
||||
#if !defined (USE_OPEN_FIRMWARE)
|
||||
/* Let's register the whole memory available only in supervisor mode */
|
||||
setup_BAT(env, 0, 0x00000000, 0x00000000, mem_size, 1, 0, 2);
|
||||
/* Avoid open firmware init call (to get a console)
|
||||
* This will make the kernel think we are a PREP machine...
|
||||
*/
|
||||
put_long(p, 0xdeadc0de);
|
||||
/* Build a real stack room */
|
||||
p = (void *)(phys_ram_base + stack_addr);
|
||||
put_long(p, stack_addr);
|
||||
p -= 32;
|
||||
env->gpr[1] -= 32;
|
||||
/* Pretend there are no residual data */
|
||||
env->gpr[3] = 0;
|
||||
#if 1
|
||||
{
|
||||
int size;
|
||||
env->gpr[4] = 0x00800000;
|
||||
size = load_initrd("initrd",
|
||||
(void *)((uint32_t)phys_ram_base + env->gpr[4]));
|
||||
if (size < 0) {
|
||||
/* No initrd */
|
||||
env->gpr[4] = env->gpr[5] = 0;
|
||||
} else {
|
||||
env->gpr[5] = size;
|
||||
boot_device = 'e';
|
||||
}
|
||||
printf("Initrd loaded at 0x%08x (%d)\n", env->gpr[4], env->gpr[5]);
|
||||
}
|
||||
#else
|
||||
env->gpr[4] = env->gpr[5] = 0;
|
||||
#endif
|
||||
/* We have to put bootinfos after the BSS
|
||||
* The BSS starts after the kernel end.
|
||||
*/
|
||||
#if 0
|
||||
p = (void *)(((uint32_t)phys_ram_base + kernel_addr +
|
||||
kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1));
|
||||
#else
|
||||
p = (void *)((uint32_t)phys_ram_base + kernel_addr + 0x400000);
|
||||
#endif
|
||||
if (loglevel > 0) {
|
||||
fprintf(logfile, "bootinfos: %p 0x%08x\n",
|
||||
p, (uint32_t)p - (uint32_t)phys_ram_base);
|
||||
} else {
|
||||
printf("bootinfos: %p 0x%08x\n",
|
||||
p, (uint32_t)p - (uint32_t)phys_ram_base);
|
||||
}
|
||||
/* Command line: let's put it after bootinfos */
|
||||
#if 0
|
||||
sprintf(p + 0x1000, "console=ttyS0,9600 root=%02x%02x mem=%dM",
|
||||
boot_devs[boot_device - 'a'].major,
|
||||
boot_devs[boot_device - 'a'].minor,
|
||||
phys_ram_size >> 20);
|
||||
#else
|
||||
sprintf(p + 0x1000, "console=ttyS0,9600 console=tty0 root=%s mem=%dM load_ramdisk=1",
|
||||
boot_devs[boot_device - 'a'].name,
|
||||
phys_ram_size >> 20);
|
||||
#endif
|
||||
env->gpr[6] = (uint32_t)p + 0x1000 - (uint32_t)phys_ram_base;
|
||||
env->gpr[7] = env->gpr[6] + strlen(p + 0x1000);
|
||||
if (loglevel > 0) {
|
||||
fprintf(logfile, "cmdline: %p 0x%08x [%s]\n",
|
||||
p + 0x1000, env->gpr[6], p + 0x1000);
|
||||
} else {
|
||||
printf("cmdline: %p 0x%08x [%s]\n",
|
||||
p + 0x1000, env->gpr[6], p + 0x1000);
|
||||
}
|
||||
/* BI_FIRST */
|
||||
p = set_bootinfo_tag(p, 0x1010, 0, 0);
|
||||
/* BI_CMD_LINE */
|
||||
p = set_bootinfo_tag(p, 0x1012, env->gpr[7] - env->gpr[6],
|
||||
(void *)(env->gpr[6] + (uint32_t)phys_ram_base));
|
||||
/* BI_MEM_SIZE */
|
||||
tmp = (void *)tmpi;
|
||||
tmp[0] = (phys_ram_size >> 24) & 0xFF;
|
||||
tmp[1] = (phys_ram_size >> 16) & 0xFF;
|
||||
tmp[2] = (phys_ram_size >> 8) & 0xFF;
|
||||
tmp[3] = phys_ram_size & 0xFF;
|
||||
p = set_bootinfo_tag(p, 0x1017, 4, tmpi);
|
||||
/* BI_INITRD */
|
||||
tmp[0] = (env->gpr[4] >> 24) & 0xFF;
|
||||
tmp[1] = (env->gpr[4] >> 16) & 0xFF;
|
||||
tmp[2] = (env->gpr[4] >> 8) & 0xFF;
|
||||
tmp[3] = env->gpr[4] & 0xFF;
|
||||
tmp[4] = (env->gpr[5] >> 24) & 0xFF;
|
||||
tmp[5] = (env->gpr[5] >> 16) & 0xFF;
|
||||
tmp[6] = (env->gpr[5] >> 8) & 0xFF;
|
||||
tmp[7] = env->gpr[5] & 0xFF;
|
||||
p = set_bootinfo_tag(p, 0x1014, 8, tmpi);
|
||||
/* BI_LAST */
|
||||
p = set_bootinfo_tag(p, 0x1011, 0, 0);
|
||||
#else
|
||||
/* Set up MMU:
|
||||
* kernel is loaded at kernel_addr and wants to be seen at 0x01000000
|
||||
*/
|
||||
setup_BAT(env, 0, 0x01000000, kernel_addr, 0x00400000, 1, 0, 2);
|
||||
{
|
||||
#if 0
|
||||
uint32_t offset =
|
||||
*((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
|
||||
#else
|
||||
uint32_t offset = 12;
|
||||
#endif
|
||||
env->nip = 0x01000000 | (kernel_addr + offset);
|
||||
printf("Start address: 0x%08x\n", env->nip);
|
||||
}
|
||||
env->gpr[1] = env->nip + (1 << 22);
|
||||
p = (void *)(phys_ram_base + stack_addr);
|
||||
put_long(p - 32, stack_addr);
|
||||
env->gpr[1] -= 32;
|
||||
printf("Kernel starts at 0x%08x stack 0x%08x\n", env->nip, env->gpr[1]);
|
||||
/* We want all lower address not to be translated */
|
||||
setup_BAT(env, 1, 0x00000000, 0x00000000, 0x010000000, 1, 1, 2);
|
||||
/* We also need a BAT to access OF */
|
||||
setup_BAT(env, 2, 0xFFFE0000, mem_size - 131072, 131072, 1, 0, 1);
|
||||
/* Setup OF entry point */
|
||||
{
|
||||
char *p;
|
||||
p = (char *)phys_ram_base + mem_size - 131072;
|
||||
/* Special opcode to call OF */
|
||||
*p++ = 0x18; *p++ = 0x00; *p++ = 0x00; *p++ = 0x02;
|
||||
/* blr */
|
||||
*p++ = 0x4E; *p++ = 0x80; *p++ = 0x00; *p++ = 0x20;
|
||||
}
|
||||
env->gpr[5] = 0xFFFE0000;
|
||||
/* Register translations */
|
||||
{
|
||||
OF_transl_t translations[3] = {
|
||||
{ 0x01000000, 0x00400000, kernel_addr, 0x00000002, },
|
||||
{ 0x00000000, 0x01000000, 0x00000000, 0x00000002, },
|
||||
{ 0xFFFE0000, 0x00020000, mem_size - (128 * 1024),
|
||||
0x00000001, },
|
||||
};
|
||||
OF_register_translations(3, translations);
|
||||
}
|
||||
/* Quite artificial, for now */
|
||||
OF_register_bus("isa", "isa");
|
||||
OF_register_serial("isa", "serial", 4, 0x3f8);
|
||||
OF_register_stdio("serial", "serial");
|
||||
/* Set up RTAS service */
|
||||
RTAS_init();
|
||||
/* Command line: let's put it just over the stack */
|
||||
#if 1
|
||||
sprintf(p, "console=ttyS0,9600 root=%02x%02x mem=%dM",
|
||||
boot_devs[boot_device - 'a'].major,
|
||||
boot_devs[boot_device - 'a'].minor,
|
||||
phys_ram_size >> 20);
|
||||
#else
|
||||
sprintf(p, "console=ttyS0,9600 root=%s mem=%dM ne2000=0x300,9",
|
||||
boot_devs[boot_device - 'a'].name,
|
||||
phys_ram_size >> 20);
|
||||
#endif
|
||||
OF_register_bootargs(p);
|
||||
#endif
|
||||
}
|
||||
|
||||
void PPC_end_init (void)
|
||||
{
|
||||
VGA_init();
|
||||
}
|
||||
789
target-ppc/op.c
789
target-ppc/op.c
File diff suppressed because it is too large
Load Diff
445
target-ppc/op_helper.c
Normal file
445
target-ppc/op_helper.c
Normal file
@ -0,0 +1,445 @@
|
||||
/*
|
||||
* PPC emulation helpers for qemu.
|
||||
*
|
||||
* Copyright (c) 2003 Jocelyn Mayer
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <math.h>
|
||||
#include "exec.h"
|
||||
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
#define MEMSUFFIX _raw
|
||||
#include "op_helper_mem.h"
|
||||
#else
|
||||
#define MEMSUFFIX _user
|
||||
#include "op_helper_mem.h"
|
||||
#define MEMSUFFIX _kernel
|
||||
#include "op_helper_mem.h"
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Exceptions processing helpers */
|
||||
void do_queue_exception_err (uint32_t exception, int error_code)
|
||||
{
|
||||
/* Queue real PPC exceptions */
|
||||
if (exception < EXCP_PPC_MAX) {
|
||||
env->exceptions |= 1 << exception;
|
||||
env->errors[exception] = error_code;
|
||||
} else {
|
||||
/* Preserve compatibility with qemu core */
|
||||
env->exceptions |= 1;
|
||||
env->exception_index = exception;
|
||||
env->error_code = error_code;
|
||||
}
|
||||
}
|
||||
|
||||
void do_queue_exception (uint32_t exception)
|
||||
{
|
||||
do_queue_exception_err(exception, 0);
|
||||
}
|
||||
|
||||
void do_check_exception_state (void)
|
||||
{
|
||||
if ((env->exceptions & 1) == 1 || check_exception_state(env)) {
|
||||
env->exceptions &= ~1;
|
||||
cpu_loop_exit();
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Helpers for "fat" micro operations */
|
||||
/* Special registers load and store */
|
||||
void do_load_cr (void)
|
||||
{
|
||||
T0 = (env->crf[0] << 28) |
|
||||
(env->crf[1] << 24) |
|
||||
(env->crf[2] << 20) |
|
||||
(env->crf[3] << 16) |
|
||||
(env->crf[4] << 12) |
|
||||
(env->crf[5] << 8) |
|
||||
(env->crf[6] << 4) |
|
||||
(env->crf[7] << 0);
|
||||
}
|
||||
|
||||
void do_store_cr (uint32_t mask)
|
||||
{
|
||||
int i, sh;
|
||||
|
||||
for (i = 0, sh = 7; i < 8; i++, sh --) {
|
||||
if (mask & (1 << sh))
|
||||
env->crf[i] = (T0 >> (sh * 4)) & 0xF;
|
||||
}
|
||||
}
|
||||
|
||||
void do_load_xer (void)
|
||||
{
|
||||
T0 = (xer_so << XER_SO) |
|
||||
(xer_ov << XER_OV) |
|
||||
(xer_ca << XER_CA) |
|
||||
(xer_bc << XER_BC);
|
||||
}
|
||||
|
||||
void do_store_xer (void)
|
||||
{
|
||||
xer_so = (T0 >> XER_SO) & 0x01;
|
||||
xer_ov = (T0 >> XER_OV) & 0x01;
|
||||
xer_ca = (T0 >> XER_CA) & 0x01;
|
||||
xer_bc = (T0 >> XER_BC) & 0x1f;
|
||||
}
|
||||
|
||||
void do_load_msr (void)
|
||||
{
|
||||
T0 = (msr_pow << MSR_POW) |
|
||||
(msr_ile << MSR_ILE) |
|
||||
(msr_ee << MSR_EE) |
|
||||
(msr_pr << MSR_PR) |
|
||||
(msr_fp << MSR_FP) |
|
||||
(msr_me << MSR_ME) |
|
||||
(msr_fe0 << MSR_FE0) |
|
||||
(msr_se << MSR_SE) |
|
||||
(msr_be << MSR_BE) |
|
||||
(msr_fe1 << MSR_FE1) |
|
||||
(msr_ip << MSR_IP) |
|
||||
(msr_ir << MSR_IR) |
|
||||
(msr_dr << MSR_DR) |
|
||||
(msr_ri << MSR_RI) |
|
||||
(msr_le << MSR_LE);
|
||||
}
|
||||
|
||||
void do_store_msr (void)
|
||||
{
|
||||
if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
|
||||
((T0 >> MSR_DR) & 0x01) != msr_dr ||
|
||||
((T0 >> MSR_PR) & 0x01) != msr_pr) {
|
||||
/* Flush all tlb when changing translation mode or privilege level */
|
||||
do_tlbia();
|
||||
}
|
||||
#if 0
|
||||
if ((T0 >> MSR_IP) & 0x01) {
|
||||
printf("Halting CPU. Stop emulation\n");
|
||||
do_queue_exception(EXCP_HLT);
|
||||
cpu_loop_exit();
|
||||
}
|
||||
#endif
|
||||
msr_pow = (T0 >> MSR_POW) & 0x03;
|
||||
msr_ile = (T0 >> MSR_ILE) & 0x01;
|
||||
msr_ee = (T0 >> MSR_EE) & 0x01;
|
||||
msr_pr = (T0 >> MSR_PR) & 0x01;
|
||||
msr_fp = (T0 >> MSR_FP) & 0x01;
|
||||
msr_me = (T0 >> MSR_ME) & 0x01;
|
||||
msr_fe0 = (T0 >> MSR_FE0) & 0x01;
|
||||
msr_se = (T0 >> MSR_SE) & 0x01;
|
||||
msr_be = (T0 >> MSR_BE) & 0x01;
|
||||
msr_fe1 = (T0 >> MSR_FE1) & 0x01;
|
||||
msr_ip = (T0 >> MSR_IP) & 0x01;
|
||||
msr_ir = (T0 >> MSR_IR) & 0x01;
|
||||
msr_dr = (T0 >> MSR_DR) & 0x01;
|
||||
msr_ri = (T0 >> MSR_RI) & 0x01;
|
||||
msr_le = (T0 >> MSR_LE) & 0x01;
|
||||
}
|
||||
|
||||
/* shift right arithmetic helper */
|
||||
void do_sraw (void)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
xer_ca = 0;
|
||||
if (T1 & 0x20) {
|
||||
ret = (-1) * (T0 >> 31);
|
||||
if (ret < 0)
|
||||
xer_ca = 1;
|
||||
} else {
|
||||
ret = (int32_t)T0 >> (T1 & 0x1f);
|
||||
if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
|
||||
xer_ca = 1;
|
||||
}
|
||||
(int32_t)T0 = ret;
|
||||
}
|
||||
|
||||
/* Floating point operations helpers */
|
||||
void do_load_fpscr (void)
|
||||
{
|
||||
/* The 32 MSB of the target fpr are undefined.
|
||||
* They'll be zero...
|
||||
*/
|
||||
union {
|
||||
double d;
|
||||
struct {
|
||||
uint32_t u[2];
|
||||
} s;
|
||||
} u;
|
||||
int i;
|
||||
|
||||
u.s.u[0] = 0;
|
||||
u.s.u[1] = 0;
|
||||
for (i = 0; i < 8; i++)
|
||||
u.s.u[1] |= env->fpscr[i] << (4 * i);
|
||||
FT0 = u.d;
|
||||
}
|
||||
|
||||
void do_store_fpscr (uint32_t mask)
|
||||
{
|
||||
/*
|
||||
* We use only the 32 LSB of the incoming fpr
|
||||
*/
|
||||
union {
|
||||
double d;
|
||||
struct {
|
||||
uint32_t u[2];
|
||||
} s;
|
||||
} u;
|
||||
int i;
|
||||
|
||||
u.d = FT0;
|
||||
if (mask & 0x80)
|
||||
env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
|
||||
for (i = 1; i < 7; i++) {
|
||||
if (mask & (1 << (7 - i)))
|
||||
env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
|
||||
}
|
||||
/* TODO: update FEX & VX */
|
||||
/* Set rounding mode */
|
||||
switch (env->fpscr[0] & 0x3) {
|
||||
case 0:
|
||||
/* Best approximation (round to nearest) */
|
||||
fesetround(FE_TONEAREST);
|
||||
break;
|
||||
case 1:
|
||||
/* Smaller magnitude (round toward zero) */
|
||||
fesetround(FE_TOWARDZERO);
|
||||
break;
|
||||
case 2:
|
||||
/* Round toward +infinite */
|
||||
fesetround(FE_UPWARD);
|
||||
break;
|
||||
case 3:
|
||||
/* Round toward -infinite */
|
||||
fesetround(FE_DOWNWARD);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void do_fctiw (void)
|
||||
{
|
||||
union {
|
||||
double d;
|
||||
uint64_t i;
|
||||
} *p = (void *)&FT1;
|
||||
|
||||
if (FT0 > (double)0x7FFFFFFF)
|
||||
p->i = 0x7FFFFFFFULL << 32;
|
||||
else if (FT0 < -(double)0x80000000)
|
||||
p->i = 0x80000000ULL << 32;
|
||||
else
|
||||
p->i = 0;
|
||||
p->i |= (uint32_t)FT0;
|
||||
FT0 = p->d;
|
||||
}
|
||||
|
||||
void do_fctiwz (void)
|
||||
{
|
||||
union {
|
||||
double d;
|
||||
uint64_t i;
|
||||
} *p = (void *)&FT1;
|
||||
int cround = fegetround();
|
||||
|
||||
fesetround(FE_TOWARDZERO);
|
||||
if (FT0 > (double)0x7FFFFFFF)
|
||||
p->i = 0x7FFFFFFFULL << 32;
|
||||
else if (FT0 < -(double)0x80000000)
|
||||
p->i = 0x80000000ULL << 32;
|
||||
else
|
||||
p->i = 0;
|
||||
p->i |= (uint32_t)FT0;
|
||||
FT0 = p->d;
|
||||
fesetround(cround);
|
||||
}
|
||||
|
||||
void do_fsqrt (void)
|
||||
{
|
||||
FT0 = sqrt(FT0);
|
||||
}
|
||||
|
||||
void do_fsqrts (void)
|
||||
{
|
||||
FT0 = (float)sqrt((float)FT0);
|
||||
}
|
||||
|
||||
void do_fres (void)
|
||||
{
|
||||
FT0 = 1.0 / FT0;
|
||||
}
|
||||
|
||||
void do_fsqrte (void)
|
||||
{
|
||||
FT0 = 1.0 / sqrt(FT0);
|
||||
}
|
||||
|
||||
void do_fsel (void)
|
||||
{
|
||||
if (FT0 >= 0)
|
||||
FT0 = FT2;
|
||||
else
|
||||
FT0 = FT1;
|
||||
}
|
||||
|
||||
void do_fcmpu (void)
|
||||
{
|
||||
env->fpscr[4] &= ~0x1;
|
||||
if (isnan(FT0) || isnan(FT1)) {
|
||||
T0 = 0x01;
|
||||
env->fpscr[4] |= 0x1;
|
||||
env->fpscr[6] |= 0x1;
|
||||
} else if (FT0 < FT1) {
|
||||
T0 = 0x08;
|
||||
} else if (FT0 > FT1) {
|
||||
T0 = 0x04;
|
||||
} else {
|
||||
T0 = 0x02;
|
||||
}
|
||||
env->fpscr[3] |= T0;
|
||||
}
|
||||
|
||||
void do_fcmpo (void)
|
||||
{
|
||||
env->fpscr[4] &= ~0x1;
|
||||
if (isnan(FT0) || isnan(FT1)) {
|
||||
T0 = 0x01;
|
||||
env->fpscr[4] |= 0x1;
|
||||
/* I don't know how to test "quiet" nan... */
|
||||
if (0 /* || ! quiet_nan(...) */) {
|
||||
env->fpscr[6] |= 0x1;
|
||||
if (!(env->fpscr[1] & 0x8))
|
||||
env->fpscr[4] |= 0x8;
|
||||
} else {
|
||||
env->fpscr[4] |= 0x8;
|
||||
}
|
||||
} else if (FT0 < FT1) {
|
||||
T0 = 0x08;
|
||||
} else if (FT0 > FT1) {
|
||||
T0 = 0x04;
|
||||
} else {
|
||||
T0 = 0x02;
|
||||
}
|
||||
env->fpscr[3] |= T0;
|
||||
}
|
||||
|
||||
void do_fabs (void)
|
||||
{
|
||||
FT0 = fabsl(FT0);
|
||||
}
|
||||
|
||||
void do_fnabs (void)
|
||||
{
|
||||
FT0 = -fabsl(FT0);
|
||||
}
|
||||
|
||||
/* Instruction cache invalidation helper */
|
||||
void do_icbi (void)
|
||||
{
|
||||
// tb_invalidate_page(T0);
|
||||
}
|
||||
|
||||
/* TLB invalidation helpers */
|
||||
void do_tlbia (void)
|
||||
{
|
||||
tlb_flush(env);
|
||||
}
|
||||
|
||||
void do_tlbie (void)
|
||||
{
|
||||
tlb_flush_page(env, T0);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Special helpers for debug */
|
||||
void dump_rfi (void)
|
||||
{
|
||||
#if 0
|
||||
printf("Return from interrupt\n");
|
||||
printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x\n",
|
||||
env->nip, env->lr, env->ctr,
|
||||
(msr_pow << MSR_POW) | (msr_ile << MSR_ILE) | (msr_ee << MSR_EE) |
|
||||
(msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_me << MSR_ME) |
|
||||
(msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | (msr_be << MSR_BE) |
|
||||
(msr_fe1 << MSR_FE1) | (msr_ip << MSR_IP) | (msr_ir << MSR_IR) |
|
||||
(msr_dr << MSR_DR) | (msr_ri << MSR_RI) | (msr_le << MSR_LE));
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i & 7) == 0)
|
||||
printf("GPR%02d:", i);
|
||||
printf(" %08x", env->gpr[i]);
|
||||
if ((i & 7) == 7)
|
||||
printf("\n");
|
||||
}
|
||||
printf("CR: 0x");
|
||||
for (i = 0; i < 8; i++)
|
||||
printf("%01x", env->crf[i]);
|
||||
printf(" [");
|
||||
for (i = 0; i < 8; i++) {
|
||||
char a = '-';
|
||||
if (env->crf[i] & 0x08)
|
||||
a = 'L';
|
||||
else if (env->crf[i] & 0x04)
|
||||
a = 'G';
|
||||
else if (env->crf[i] & 0x02)
|
||||
a = 'E';
|
||||
printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
|
||||
}
|
||||
printf(" ] ");
|
||||
}
|
||||
printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
|
||||
printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
|
||||
#endif
|
||||
}
|
||||
|
||||
void dump_store_sr (int srnum)
|
||||
{
|
||||
#if 0
|
||||
printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void _dump_store_bat (char ID, int ul, int nr)
|
||||
{
|
||||
printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
|
||||
ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
|
||||
}
|
||||
|
||||
void dump_store_ibat (int ul, int nr)
|
||||
{
|
||||
_dump_store_bat('I', ul, nr);
|
||||
}
|
||||
|
||||
void dump_store_dbat (int ul, int nr)
|
||||
{
|
||||
_dump_store_bat('D', ul, nr);
|
||||
}
|
||||
|
||||
void dump_store_tb (int ul)
|
||||
{
|
||||
printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
|
||||
}
|
||||
|
||||
void dump_update_tb(uint32_t param)
|
||||
{
|
||||
#if 0
|
||||
printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
|
||||
#endif
|
||||
}
|
||||
|
||||
44
target-ppc/op_helper_mem.h
Normal file
44
target-ppc/op_helper_mem.h
Normal file
@ -0,0 +1,44 @@
|
||||
void glue(do_lsw, MEMSUFFIX) (int dst)
|
||||
{
|
||||
uint32_t tmp;
|
||||
int sh;
|
||||
|
||||
if (loglevel > 0) {
|
||||
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
|
||||
__func__, T0, T1, dst);
|
||||
}
|
||||
for (; T1 > 3; T1 -= 4, T0 += 4) {
|
||||
ugpr(dst++) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
|
||||
if (dst == 32)
|
||||
dst = 0;
|
||||
}
|
||||
if (T1 > 0) {
|
||||
tmp = 0;
|
||||
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
|
||||
tmp |= glue(_ldub, MEMSUFFIX)((void *)T0, ACCESS_INT) << sh;
|
||||
}
|
||||
ugpr(dst) = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
void glue(do_stsw, MEMSUFFIX) (int src)
|
||||
{
|
||||
int sh;
|
||||
|
||||
if (loglevel > 0) {
|
||||
fprintf(logfile, "%s: addr=0x%08x count=%d reg=%d\n",
|
||||
__func__, T0, T1, src);
|
||||
}
|
||||
for (; T1 > 3; T1 -= 4, T0 += 4) {
|
||||
glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src++), ACCESS_INT);
|
||||
if (src == 32)
|
||||
src = 0;
|
||||
}
|
||||
if (T1 > 0) {
|
||||
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
|
||||
glue(_stb, MEMSUFFIX)((void *)T0, (ugpr(src) >> sh) & 0xFF,
|
||||
ACCESS_INT);
|
||||
}
|
||||
}
|
||||
|
||||
#undef MEMSUFFIX
|
||||
187
target-ppc/op_mem.h
Normal file
187
target-ppc/op_mem.h
Normal file
@ -0,0 +1,187 @@
|
||||
/* External helpers */
|
||||
void glue(do_lsw, MEMSUFFIX) (int dst);
|
||||
void glue(do_stsw, MEMSUFFIX) (int src);
|
||||
|
||||
/* Internal helpers for sign extension and byte-reverse */
|
||||
static inline uint32_t glue(_ld16x, MEMSUFFIX) (void *EA, int type)
|
||||
{
|
||||
return s_ext16(glue(_lduw, MEMSUFFIX)(EA, type));
|
||||
}
|
||||
|
||||
static inline uint16_t glue(_ld16r, MEMSUFFIX) (void *EA, int type)
|
||||
{
|
||||
uint16_t tmp = glue(_lduw, MEMSUFFIX)(EA, type);
|
||||
return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
|
||||
}
|
||||
|
||||
static inline uint32_t glue(_ld32r, MEMSUFFIX) (void *EA, int type)
|
||||
{
|
||||
uint32_t tmp = glue(_ldl, MEMSUFFIX)(EA, type);
|
||||
return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
|
||||
((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
|
||||
}
|
||||
|
||||
static inline void glue(_st16r, MEMSUFFIX) (void *EA, uint16_t data, int type)
|
||||
{
|
||||
uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
|
||||
glue(_stw, MEMSUFFIX)(EA, tmp, type);
|
||||
}
|
||||
|
||||
static inline void glue(_st32r, MEMSUFFIX) (void *EA, uint32_t data, int type)
|
||||
{
|
||||
uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) |
|
||||
((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24);
|
||||
glue(_stl, MEMSUFFIX)(EA, tmp, type);
|
||||
}
|
||||
|
||||
/*** Integer load ***/
|
||||
#define PPC_LD_OP(name, op) \
|
||||
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
|
||||
{ \
|
||||
T1 = glue(op, MEMSUFFIX)((void *)T0, ACCESS_INT); \
|
||||
RETURN(); \
|
||||
}
|
||||
|
||||
#define PPC_ST_OP(name, op) \
|
||||
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
|
||||
{ \
|
||||
glue(op, MEMSUFFIX)((void *)T0, T1, ACCESS_INT); \
|
||||
RETURN(); \
|
||||
}
|
||||
|
||||
PPC_LD_OP(bz, _ldub);
|
||||
PPC_LD_OP(ha, _ld16x);
|
||||
PPC_LD_OP(hz, _lduw);
|
||||
PPC_LD_OP(wz, _ldl);
|
||||
|
||||
/*** Integer store ***/
|
||||
PPC_ST_OP(b, _stb);
|
||||
PPC_ST_OP(h, _stw);
|
||||
PPC_ST_OP(w, _stl);
|
||||
|
||||
/*** Integer load and store with byte reverse ***/
|
||||
PPC_LD_OP(hbr, _ld16r);
|
||||
PPC_LD_OP(wbr, _ld32r);
|
||||
PPC_ST_OP(hbr, _st16r);
|
||||
PPC_ST_OP(wbr, _st32r);
|
||||
|
||||
/*** Integer load and store multiple ***/
|
||||
PPC_OP(glue(lmw, MEMSUFFIX))
|
||||
{
|
||||
int dst = PARAM(1);
|
||||
|
||||
for (; dst < 32; dst++, T0 += 4) {
|
||||
ugpr(dst) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
|
||||
}
|
||||
RETURN();
|
||||
}
|
||||
|
||||
PPC_OP(glue(stmw, MEMSUFFIX))
|
||||
{
|
||||
int src = PARAM(1);
|
||||
|
||||
for (; src < 32; src++, T0 += 4) {
|
||||
glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src), ACCESS_INT);
|
||||
}
|
||||
RETURN();
|
||||
}
|
||||
|
||||
/*** Integer load and store strings ***/
|
||||
PPC_OP(glue(lswi, MEMSUFFIX))
|
||||
{
|
||||
glue(do_lsw, MEMSUFFIX)(PARAM(1));
|
||||
RETURN();
|
||||
}
|
||||
|
||||
/* PPC32 specification says we must generate an exception if
|
||||
* rA is in the range of registers to be loaded.
|
||||
* In an other hand, IBM says this is valid, but rA won't be loaded.
|
||||
* For now, I'll follow the spec...
|
||||
*/
|
||||
PPC_OP(glue(lswx, MEMSUFFIX))
|
||||
{
|
||||
if (T1 > 0) {
|
||||
if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
|
||||
(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
|
||||
do_queue_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
|
||||
do_process_exceptions();
|
||||
} else {
|
||||
glue(do_lsw, MEMSUFFIX)(PARAM(1));
|
||||
}
|
||||
}
|
||||
RETURN();
|
||||
}
|
||||
|
||||
PPC_OP(glue(stsw, MEMSUFFIX))
|
||||
{
|
||||
glue(do_stsw, MEMSUFFIX)(PARAM(1));
|
||||
RETURN();
|
||||
}
|
||||
|
||||
/*** Floating-point store ***/
|
||||
#define PPC_STF_OP(name, op) \
|
||||
PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
|
||||
{ \
|
||||
glue(op, MEMSUFFIX)((void *)T0, FT1); \
|
||||
RETURN(); \
|
||||
}
|
||||
|
||||
PPC_STF_OP(fd, stfq);
|
||||
PPC_STF_OP(fs, stfl);
|
||||
|
||||
/*** Floating-point load ***/
|
||||
#define PPC_LDF_OP(name, op) \
|
||||
PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
|
||||
{ \
|
||||
FT1 = glue(op, MEMSUFFIX)((void *)T0); \
|
||||
RETURN(); \
|
||||
}
|
||||
|
||||
PPC_LDF_OP(fd, ldfq);
|
||||
PPC_LDF_OP(fs, ldfl);
|
||||
|
||||
/* Store with reservation */
|
||||
PPC_OP(glue(stwcx, MEMSUFFIX))
|
||||
{
|
||||
if (T0 & 0x03) {
|
||||
do_queue_exception(EXCP_ALIGN);
|
||||
do_process_exceptions();
|
||||
} else {
|
||||
if (regs->reserve != T0) {
|
||||
env->crf[0] = xer_ov;
|
||||
} else {
|
||||
glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_RES);
|
||||
env->crf[0] = xer_ov | 0x02;
|
||||
}
|
||||
}
|
||||
regs->reserve = 0;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
PPC_OP(glue(dcbz, MEMSUFFIX))
|
||||
{
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x00), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x04), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x08), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x0C), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x10), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x14), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x18), 0, ACCESS_INT);
|
||||
glue(_stl, MEMSUFFIX)((void *)(T0 + 0x1C), 0, ACCESS_INT);
|
||||
RETURN();
|
||||
}
|
||||
|
||||
/* External access */
|
||||
PPC_OP(glue(eciwx, MEMSUFFIX))
|
||||
{
|
||||
T1 = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_EXT);
|
||||
RETURN();
|
||||
}
|
||||
|
||||
PPC_OP(glue(ecowx, MEMSUFFIX))
|
||||
{
|
||||
glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_EXT);
|
||||
RETURN();
|
||||
}
|
||||
|
||||
#undef MEMSUFFIX
|
||||
@ -18,56 +18,67 @@
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* General purpose registers moves */
|
||||
void OPPROTO glue(op_load_gpr_T0_gpr, REG)(void)
|
||||
{
|
||||
T0 = regs->gpr[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_load_gpr_T1_gpr, REG)(void)
|
||||
{
|
||||
T1 = regs->gpr[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_load_gpr_T2_gpr, REG)(void)
|
||||
{
|
||||
T2 = regs->gpr[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_T0_gpr_gpr, REG)(void)
|
||||
{
|
||||
regs->gpr[REG] = T0;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_T1_gpr_gpr, REG)(void)
|
||||
{
|
||||
regs->gpr[REG] = T1;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_T2_gpr_gpr, REG)(void)
|
||||
{
|
||||
regs->gpr[REG] = T2;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
#if REG <= 7
|
||||
|
||||
/* Condition register moves */
|
||||
void OPPROTO glue(op_load_crf_T0_crf, REG)(void)
|
||||
{
|
||||
T0 = regs->crf[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_load_crf_T1_crf, REG)(void)
|
||||
{
|
||||
T1 = regs->crf[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_T0_crf_crf, REG)(void)
|
||||
{
|
||||
regs->crf[REG] = T0;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_T1_crf_crf, REG)(void)
|
||||
{
|
||||
regs->crf[REG] = T1;
|
||||
RETURN();
|
||||
}
|
||||
|
||||
/* Floating point condition and status register moves */
|
||||
@ -117,8 +128,6 @@ void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void)
|
||||
|
||||
#endif /* REG <= 7 */
|
||||
|
||||
/* float moves */
|
||||
|
||||
/* floating point registers moves */
|
||||
void OPPROTO glue(op_load_fpr_FT0_fpr, REG)(void)
|
||||
{
|
||||
@ -156,4 +165,22 @@ void OPPROTO glue(op_store_FT2_fpr_fpr, REG)(void)
|
||||
RETURN();
|
||||
}
|
||||
|
||||
#if REG <= 15
|
||||
/* Segment register moves */
|
||||
void OPPROTO glue(op_load_sr, REG)(void)
|
||||
{
|
||||
T0 = env->sr[REG];
|
||||
RETURN();
|
||||
}
|
||||
|
||||
void OPPROTO glue(op_store_sr, REG)(void)
|
||||
{
|
||||
#if defined (DEBUG_OP)
|
||||
dump_store_sr(REG);
|
||||
#endif
|
||||
env->sr[REG] = T0;
|
||||
RETURN();
|
||||
}
|
||||
#endif
|
||||
|
||||
#undef REG
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user