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target-microblaze: Allow the stack protection to be disabled
Microblaze stack protection is configurable and isn't always enabled. This patch allows the stack protection to be disabled from the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -59,6 +59,11 @@ typedef struct MicroBlazeCPU {
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uint32_t base_vectors;
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/*< public >*/
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/* Microblaze Configuration Settings */
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struct {
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bool stackprot;
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} cfg;
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CPUMBState env;
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} MicroBlazeCPU;
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@ -114,6 +114,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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| PVR2_USE_FPU2_MASK \
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| PVR2_FPU_EXC_MASK \
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| 0;
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env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0;
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env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
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env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
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@ -156,6 +159,8 @@ static const VMStateDescription vmstate_mb_cpu = {
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static Property mb_properties[] = {
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DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
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DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
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true),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -128,6 +128,7 @@ typedef struct CPUMBState CPUMBState;
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#define PVR0_FAULT 0x00100000
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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#define PVR0_SPROT_MASK 0x00000001
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/* User 2 PVR mask */
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#define PVR1_USER2_MASK 0xFFFFFFFF
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@ -862,7 +862,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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int stackprot = 0;
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/* All load/stores use ra. */
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if (dc->ra == 1) {
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if (dc->ra == 1 && dc->cpu->cfg.stackprot) {
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stackprot = 1;
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}
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@ -875,7 +875,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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return &cpu_R[dc->ra];
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}
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if (dc->rb == 1) {
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if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
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stackprot = 1;
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}
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