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target/xtensa: SMP updates and various fixes

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- fix CPU wakeup on runstall changes; expose runstall as an IRQ line;
 - place mini-bootloader at the BSP reset vector;
 - expose CPU core frequency in XTFPGA board FPGA register;
 - rearrange access to external interrupts of xtensa cores;
 - add MX interrupt distributor and use it on SMP XTFPGA boards;
 - add test_mmuhifi_c3 xtensa core variant;
 - raise number of CPUs that can be instantiated on XTFPGA boards.
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Merge remote-tracking branch 'remotes/xtensa/tags/20190204-xtensa' into staging

target/xtensa: SMP updates and various fixes

- fix CPU wakeup on runstall changes; expose runstall as an IRQ line;
- place mini-bootloader at the BSP reset vector;
- expose CPU core frequency in XTFPGA board FPGA register;
- rearrange access to external interrupts of xtensa cores;
- add MX interrupt distributor and use it on SMP XTFPGA boards;
- add test_mmuhifi_c3 xtensa core variant;
- raise number of CPUs that can be instantiated on XTFPGA boards.

# gpg: Signature made Mon 04 Feb 2019 18:59:32 GMT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190204-xtensa:
  hw/xtensa: xtfpga: raise CPU number limit
  target/xtensa: add test_mmuhifi_c3 core
  hw/xtensa: xtfpga: use MX PIC for SMP
  target/xtensa: add MX interrupt controller
  target/xtensa: expose core runstall as an IRQ line
  target/xtensa: rearrange access to external interrupts
  target/xtensa: drop function xtensa_timer_irq
  target/xtensa: fix access to the INTERRUPT SR
  hw/xtensa: xtfpga: use core frequency
  hw/xtensa: xtfpga: fix bootloader placement in SMP
  target/xtensa: add qemu_cpu_kick to xtensa_runstall

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-02-05 09:35:53 +00:00
commit 9ae805637a
16 changed files with 37480 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/xtensa/Makefile.objs
View File

@ -1,3 +1,4 @@
obj-y += mx_pic.o
obj-y += pic_cpu.o
obj-y += sim.o
obj-y += xtensa_memory.o

354
hw/xtensa/mx_pic.c Normal file
View File

@ -0,0 +1,354 @@
/*
* Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/xtensa/mx_pic.h"
#include "qemu/log.h"
#define MX_MAX_CPU 32
#define MX_MAX_IRQ 32
#define MIROUT 0x0
#define MIPICAUSE 0x100
#define MIPISET 0x140
#define MIENG 0x180
#define MIENGSET 0x184
#define MIASG 0x188
#define MIASGSET 0x18c
#define MIPIPART 0x190
#define SYSCFGID 0x1a0
#define MPSCORE 0x200
#define CCON 0x220
struct XtensaMxPic {
unsigned n_cpu;
unsigned n_irq;
uint32_t ext_irq_state;
uint32_t mieng;
uint32_t miasg;
uint32_t mirout[MX_MAX_IRQ];
uint32_t mipipart;
uint32_t runstall;
qemu_irq *irq_inputs;
struct XtensaMxPicCpu {
XtensaMxPic *mx;
qemu_irq *irq;
qemu_irq runstall;
uint32_t mipicause;
uint32_t mirout_cache;
uint32_t irq_state_cache;
uint32_t ccon;
MemoryRegion reg;
} cpu[MX_MAX_CPU];
};
static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset,
unsigned size)
{
struct XtensaMxPicCpu *mx_cpu = opaque;
struct XtensaMxPic *mx = mx_cpu->mx;
if (offset < MIROUT + MX_MAX_IRQ) {
return mx->mirout[offset - MIROUT];
} else if (offset >= MIPICAUSE && offset < MIPICAUSE + MX_MAX_CPU) {
return mx->cpu[offset - MIPICAUSE].mipicause;
} else {
switch (offset) {
case MIENG:
return mx->mieng;
case MIASG:
return mx->miasg;
case MIPIPART:
return mx->mipipart;
case SYSCFGID:
return ((mx->n_cpu - 1) << 18) | (mx_cpu - mx->cpu);
case MPSCORE:
return mx->runstall;
case CCON:
return mx_cpu->ccon;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"unknown RER in MX PIC range: 0x%08x\n",
(uint32_t)offset);
return 0;
}
}
}
static uint32_t xtensa_mx_pic_get_ipi_for_cpu(const XtensaMxPic *mx,
unsigned cpu)
{
uint32_t mipicause = mx->cpu[cpu].mipicause;
uint32_t mipipart = mx->mipipart;
return (((mipicause & 1) << (mipipart & 3)) |
((mipicause & 0x000e) != 0) << ((mipipart >> 2) & 3) |
((mipicause & 0x00f0) != 0) << ((mipipart >> 4) & 3) |
((mipicause & 0xff00) != 0) << ((mipipart >> 6) & 3)) & 0x7;
}
static uint32_t xtensa_mx_pic_get_ext_irq_for_cpu(const XtensaMxPic *mx,
unsigned cpu)
{
return ((((mx->ext_irq_state & mx->mieng) | mx->miasg) &
mx->cpu[cpu].mirout_cache) << 2) |
xtensa_mx_pic_get_ipi_for_cpu(mx, cpu);
}
static void xtensa_mx_pic_update_cpu(XtensaMxPic *mx, unsigned cpu)
{
uint32_t irq = xtensa_mx_pic_get_ext_irq_for_cpu(mx, cpu);
uint32_t changed_irq = mx->cpu[cpu].irq_state_cache ^ irq;
unsigned i;
qemu_log_mask(CPU_LOG_INT, "%s: CPU %d, irq: %08x, changed_irq: %08x\n",
__func__, cpu, irq, changed_irq);
mx->cpu[cpu].irq_state_cache = irq;
for (i = 0; changed_irq; ++i) {
uint32_t mask = 1u << i;
if (changed_irq & mask) {
changed_irq ^= mask;
qemu_set_irq(mx->cpu[cpu].irq[i], irq & mask);
}
}
}
static void xtensa_mx_pic_update_all(XtensaMxPic *mx)
{
unsigned cpu;
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
static void xtensa_mx_pic_ext_reg_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
struct XtensaMxPicCpu *mx_cpu = opaque;
struct XtensaMxPic *mx = mx_cpu->mx;
unsigned cpu;
if (offset < MIROUT + mx->n_irq) {
mx->mirout[offset - MIROUT] = v;
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
uint32_t mask = 1u << (offset - MIROUT);
if (!(mx->cpu[cpu].mirout_cache & mask) != !(v & (1u << cpu))) {
mx->cpu[cpu].mirout_cache ^= mask;
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
} else if (offset >= MIPICAUSE && offset < MIPICAUSE + mx->n_cpu) {
cpu = offset - MIPICAUSE;
mx->cpu[cpu].mipicause &= ~v;
xtensa_mx_pic_update_cpu(mx, cpu);
} else if (offset >= MIPISET && offset < MIPISET + 16) {
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
if (v & (1u << cpu)) {
mx->cpu[cpu].mipicause |= 1u << (offset - MIPISET);
xtensa_mx_pic_update_cpu(mx, cpu);
}
}
} else {
uint32_t change = 0;
uint32_t oldv, newv;
const char *name = "???";
switch (offset) {
case MIENG:
change = mx->mieng & v;
oldv = mx->mieng;
mx->mieng &= ~v;
newv = mx->mieng;
name = "MIENG";
break;
case MIENGSET:
change = ~mx->mieng & v;
oldv = mx->mieng;
mx->mieng |= v;
newv = mx->mieng;
name = "MIENG";
break;
case MIASG:
change = mx->miasg & v;
oldv = mx->miasg;
mx->miasg &= ~v;
newv = mx->miasg;
name = "MIASG";
break;
case MIASGSET:
change = ~mx->miasg & v;
oldv = mx->miasg;
mx->miasg |= v;
newv = mx->miasg;
name = "MIASG";
break;
case MIPIPART:
change = mx->mipipart ^ v;
oldv = mx->mipipart;
mx->mipipart = v;
newv = mx->mipipart;
name = "MIPIPART";
break;
case MPSCORE:
change = mx->runstall ^ v;
oldv = mx->runstall;
mx->runstall = v;
newv = mx->runstall;
name = "RUNSTALL";
for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
if (change & (1u << cpu)) {
qemu_set_irq(mx->cpu[cpu].runstall, v & (1u << cpu));
}
}
break;
case CCON:
mx_cpu->ccon = v & 0x1;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"unknown WER in MX PIC range: 0x%08x = 0x%08x\n",
(uint32_t)offset, (uint32_t)v);
break;
}
if (change) {
qemu_log_mask(CPU_LOG_INT,
"%s: %s changed by CPU %d: %08x -> %08x\n",
__func__, name, (int)(mx_cpu - mx->cpu),
oldv, newv);
xtensa_mx_pic_update_all(mx);
}
}
}
static const MemoryRegionOps xtensa_mx_pic_ops = {
.read = xtensa_mx_pic_ext_reg_read,
.write = xtensa_mx_pic_ext_reg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.unaligned = true,
},
};
MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
qemu_irq *irq,
qemu_irq runstall)
{
struct XtensaMxPicCpu *mx_cpu = mx->cpu + mx->n_cpu;
mx_cpu->mx = mx;
mx_cpu->irq = irq;
mx_cpu->runstall = runstall;
memory_region_init_io(&mx_cpu->reg, NULL, &xtensa_mx_pic_ops, mx_cpu,
"mx_pic", 0x280);
++mx->n_cpu;
return &mx_cpu->reg;
}
static void xtensa_mx_pic_set_irq(void *opaque, int irq, int active)
{
XtensaMxPic *mx = opaque;
if (irq < mx->n_irq) {
uint32_t old_irq_state = mx->ext_irq_state;
if (active) {
mx->ext_irq_state |= 1u << irq;
} else {
mx->ext_irq_state &= ~(1u << irq);
}
if (old_irq_state != mx->ext_irq_state) {
qemu_log_mask(CPU_LOG_INT,
"%s: IRQ %d, active: %d, ext_irq_state: %08x -> %08x\n",
__func__, irq, active,
old_irq_state, mx->ext_irq_state);
xtensa_mx_pic_update_all(mx);
}
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: IRQ %d out of range\n",
__func__, irq);
}
}
XtensaMxPic *xtensa_mx_pic_init(unsigned n_irq)
{
XtensaMxPic *mx = calloc(1, sizeof(XtensaMxPic));
mx->n_irq = n_irq + 1;
mx->irq_inputs = qemu_allocate_irqs(xtensa_mx_pic_set_irq, mx,
mx->n_irq);
return mx;
}
void xtensa_mx_pic_reset(void *opaque)
{
XtensaMxPic *mx = opaque;
unsigned i;
mx->ext_irq_state = 0;
mx->mieng = mx->n_irq < 32 ? (1u << mx->n_irq) - 1 : ~0u;
mx->miasg = 0;
mx->mipipart = 0;
for (i = 0; i < mx->n_irq; ++i) {
mx->mirout[i] = 1;
}
for (i = 0; i < mx->n_cpu; ++i) {
mx->cpu[i].mipicause = 0;
mx->cpu[i].mirout_cache = i ? 0 : mx->mieng;
mx->cpu[i].irq_state_cache = 0;
mx->cpu[i].ccon = 0;
}
mx->runstall = (1u << mx->n_cpu) - 2;
for (i = 0; i < mx->n_cpu; ++i) {
qemu_set_irq(mx->cpu[i].runstall, i > 0);
}
}
qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx)
{
return mx->irq_inputs + 1;
}

47
hw/xtensa/pic_cpu.c
View File

@ -68,36 +68,37 @@ static void xtensa_set_irq(void *opaque, int irq, int active)
uint32_t irq_bit = 1 << irq;
if (active) {
env->sregs[INTSET] |= irq_bit;
atomic_or(&env->sregs[INTSET], irq_bit);
} else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
env->sregs[INTSET] &= ~irq_bit;
atomic_and(&env->sregs[INTSET], ~irq_bit);
}
check_interrupts(env);
}
}
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
{
qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
}
static void xtensa_ccompare_cb(void *opaque)
{
XtensaCcompareTimer *ccompare = opaque;
CPUXtensaState *env = ccompare->env;
unsigned i = ccompare - env->ccompare;
xtensa_timer_irq(env, i, 1);
qemu_set_irq(env->irq_inputs[env->config->timerint[i]], 1);
}
static void xtensa_set_runstall(void *opaque, int irq, int active)
{
CPUXtensaState *env = opaque;
xtensa_runstall(env, active);
}
void xtensa_irq_init(CPUXtensaState *env)
{
env->irq_inputs = (void **)qemu_allocate_irqs(
xtensa_set_irq, env, env->config->ninterrupt);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
unsigned i;
unsigned i;
env->irq_inputs = qemu_allocate_irqs(xtensa_set_irq, env,
env->config->ninterrupt);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
env->ccount_base = env->sregs[CCOUNT];
for (i = 0; i < env->config->nccompare; ++i) {
@ -106,16 +107,20 @@ void xtensa_irq_init(CPUXtensaState *env)
xtensa_ccompare_cb, env->ccompare + i);
}
}
for (i = 0; i < env->config->nextint; ++i) {
unsigned irq = env->config->extint[i];
env->ext_irq_inputs[i] = env->irq_inputs[irq];
}
env->runstall_irq = qemu_allocate_irq(xtensa_set_runstall, env, 0);
}
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
qemu_irq *xtensa_get_extints(CPUXtensaState *env)
{
if (extint < env->config->nextint) {
unsigned irq = env->config->extint[extint];
return env->irq_inputs[irq];
} else {
qemu_log("%s: trying to acquire invalid external interrupt %d\n",
__func__, extint);
return NULL;
}
return env->ext_irq_inputs;
}
qemu_irq xtensa_get_runstall(CPUXtensaState *env)
{
return env->runstall_irq;
}

67
hw/xtensa/xtfpga.c
View File

@ -45,6 +45,7 @@
#include "qemu/option.h"
#include "bootparam.h"
#include "xtensa_memory.h"
#include "hw/xtensa/mx_pic.h"
typedef struct XtfpgaFlashDesc {
hwaddr base;
@ -61,6 +62,7 @@ typedef struct XtfpgaBoardDesc {
typedef struct XtfpgaFpgaState {
MemoryRegion iomem;
uint32_t freq;
uint32_t leds;
uint32_t switches;
} XtfpgaFpgaState;
@ -83,7 +85,7 @@ static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
return 0x09272011;
case 0x4: /*processor clock frequency, Hz*/
return 10000000;
return s->freq;
case 0x8: /*LEDs (off = 0, on = 1)*/
return s->leds;
@ -119,13 +121,14 @@ static const MemoryRegionOps xtfpga_fpga_ops = {
};
static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
hwaddr base)
hwaddr base, uint32_t freq)
{
XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
"xtfpga.fpga", 0x10000);
"xtfpga.fpga", 0x10000);
memory_region_add_subregion(address_space, base, &s->iomem);
s->freq = freq;
xtfpga_fpga_reset(s);
qemu_register_reset(xtfpga_fpga_reset, s);
return s;
@ -223,6 +226,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
XtensaCPU *cpu = NULL;
CPUXtensaState *env = NULL;
MemoryRegion *system_io;
XtensaMxPic *mx_pic = NULL;
qemu_irq *extints;
DriveInfo *dinfo;
pflash_t *flash = NULL;
QemuOpts *machine_opts = qemu_get_machine_opts();
@ -231,19 +236,45 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
const unsigned system_io_size = 224 * MiB;
uint32_t freq = 10000000;
int n;
if (smp_cpus > 1) {
mx_pic = xtensa_mx_pic_init(31);
qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
}
for (n = 0; n < smp_cpus; n++) {
cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
CPUXtensaState *cenv = NULL;
env->sregs[PRID] = n;
cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
cenv = &cpu->env;
if (!env) {
env = cenv;
freq = env->config->clock_freq_khz * 1000;
}
if (mx_pic) {
MemoryRegion *mx_eri;
mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
xtensa_get_extints(cenv),
xtensa_get_runstall(cenv));
memory_region_add_subregion(xtensa_get_er_region(cenv),
0, mx_eri);
}
cenv->sregs[PRID] = n;
xtensa_select_static_vectors(cenv, n != 0);
qemu_register_reset(xtfpga_reset, cpu);
/* Need MMU initialized prior to ELF loading,
* so that ELF gets loaded into virtual addresses
*/
cpu_reset(CPU(cpu));
}
if (smp_cpus > 1) {
extints = xtensa_mx_pic_get_extints(mx_pic);
} else {
extints = xtensa_get_extints(env);
}
if (env) {
XtensaMemory sysram = env->config->sysram;
@ -272,14 +303,14 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
system_io, 0, system_io_size);
memory_region_add_subregion(system_memory, board->io[1], io);
}
xtfpga_fpga_init(system_io, 0x0d020000);
xtfpga_fpga_init(system_io, 0x0d020000, freq);
if (nd_table[0].used) {
xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
xtensa_get_extint(env, 1), nd_table);
extints[1], nd_table);
}
serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
serial_mm_init(system_io, 0x0d050020, 2, extints[0],
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
@ -568,7 +599,7 @@ static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
mc->init = xtfpga_lx60_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
mc->default_ram_size = 64 * MiB;
}
@ -585,7 +616,7 @@ static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
mc->init = xtfpga_lx60_nommu_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
mc->default_ram_size = 64 * MiB;
}
@ -602,7 +633,7 @@ static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
mc->init = xtfpga_lx200_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
mc->default_ram_size = 96 * MiB;
}
@ -619,7 +650,7 @@ static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
mc->init = xtfpga_lx200_nommu_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
mc->default_ram_size = 96 * MiB;
}
@ -636,7 +667,7 @@ static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
mc->init = xtfpga_ml605_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
}
@ -653,7 +684,7 @@ static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
mc->init = xtfpga_ml605_nommu_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
mc->default_ram_size = 256 * MiB;
}
@ -670,7 +701,7 @@ static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
mc->init = xtfpga_kc705_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
}
@ -687,7 +718,7 @@ static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
mc->init = xtfpga_kc705_nommu_init;
mc->max_cpus = 4;
mc->max_cpus = 32;
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
mc->default_ram_size = 256 * MiB;
}

44
include/hw/xtensa/mx_pic.h Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _XTENSA_MX_PIC_H
#define _XTENSA_MX_PIC_H
#include "exec/memory.h"
#include "hw/irq.h"
struct XtensaMxPic;
typedef struct XtensaMxPic XtensaMxPic;
XtensaMxPic *xtensa_mx_pic_init(unsigned n_extint);
void xtensa_mx_pic_reset(void *opaque);
MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
qemu_irq *irq,
qemu_irq runstall);
qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx);
#endif

1
target/xtensa/Makefile.objs
View File

@ -4,6 +4,7 @@ obj-y += core-de212.o
obj-y += core-fsf.o
obj-y += core-sample_controller.o
obj-y += core-test_kc705_be.o
obj-y += core-test_mmuhifi_c3.o
obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o
obj-y += xtensa-isa.o
obj-y += translate.o op_helper.o helper.o cpu.o

53
target/xtensa/core-test_mmuhifi_c3.c Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2019, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "qemu/host-utils.h"
#include "core-test_mmuhifi_c3/core-isa.h"
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_test_mmuhifi_c3
#include "core-test_mmuhifi_c3/xtensa-modules.inc.c"
static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
.name = "test_mmuhifi_c3",
.options = XTENSA_OPTIONS,
.gdb_regmap = {
.reg = {
#include "core-test_mmuhifi_c3/gdb-config.inc.c"
}
},
.isa_internal = &xtensa_modules,
.clock_freq_khz = 40000,
DEFAULT_SECTIONS
};
REGISTER_CORE(test_mmuhifi_c3)

384
target/xtensa/core-test_mmuhifi_c3/core-isa.h Normal file
View File

@ -0,0 +1,384 @@
/*
* Xtensa processor core configuration information.
*
* This file is subject to the terms and conditions of version 2.1 of the GNU
* Lesser General Public License as published by the Free Software Foundation.
*
* Copyright (c) 1999-2009 Tensilica Inc.
*/
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_FP 0 /* floating point pkg */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 800000 /* sw version of this header */
#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3"
#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC1B3CBFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x10405A6A /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX3.0.0" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 230000 /* major*100+minor */
#define XCHAL_HW_REL_LX3 1
#define XCHAL_HW_REL_LX3_0 1
#define XCHAL_HW_REL_LX3_0_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 230000 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 8
#define XCHAL_DCACHE_SETWIDTH 8
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 2
#define XCHAL_DCACHE_WAYS 2
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 8
#define XCHAL_DCACHE_ACCESS_SIZE 8
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 12 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x00000FFF
#define XCHAL_INTLEVEL2_MASK 0x00000000
#define XCHAL_INTLEVEL3_MASK 0x00000000
#define XCHAL_INTLEVEL4_MASK 0x00000000
#define XCHAL_INTLEVEL5_MASK 0x00000000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00000000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00000FFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00000FFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 1
#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000004
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B
#define XCHAL_INTTYPE_MASK_TIMER 0x00000140
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 8 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/* Interrupt numbers for levels at which only one interrupt is configured: */
/* (There are many interrupts each at level(s) 1.) */
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x00000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0xD0000340
#define XCHAL_USER_VECTOR_PADDR 0x00000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000280
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000280
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

140
target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c Normal file
View File

@ -0,0 +1,140 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* idx ofs bi sz al targno flags cp typ group name */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
"03:04:84:b2","03:04:84:a7",0,0,0,0)
XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
"03:04:94:b2","03:04:94:a7",0,0,0,0)
XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
"03:04:04:c3","03:04:04:c1",0,0,0,0)
XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
"03:04:14:c3","03:04:44:c1",0,0,0,0)
XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
"03:04:24:c3","03:04:84:c1",0,0,0,0)
XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
"03:04:34:c3","03:04:c4:c1",0,0,0,0)
XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
XTREG_END

36403
target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c Normal file
View File

File diff suppressed because it is too large Load Diff

8
target/xtensa/cpu.h
View File

@ -483,7 +483,9 @@ typedef struct CPUXtensaState {
AddressSpace *address_space_er;
MemoryRegion *system_er;
int pending_irq_level; /* level of last raised IRQ */
void **irq_inputs;
qemu_irq *irq_inputs;
qemu_irq ext_irq_inputs[MAX_NINTERRUPT];
qemu_irq runstall_irq;
XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
uint64_t time_base;
uint64_t ccount_time;
@ -569,8 +571,8 @@ void xtensa_register_core(XtensaConfigList *node);
void xtensa_sim_open_console(Chardev *chr);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
qemu_irq *xtensa_get_extints(CPUXtensaState *env);
qemu_irq xtensa_get_runstall(CPUXtensaState *env);
int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void xtensa_sync_window_from_phys(CPUXtensaState *env);

13
target/xtensa/exc_helper.c
View File

@ -127,6 +127,19 @@ void HELPER(check_interrupts)(CPUXtensaState *env)
qemu_mutex_unlock_iothread();
}
void HELPER(intset)(CPUXtensaState *env, uint32_t v)
{
atomic_or(&env->sregs[INTSET],
v & env->config->inttype_mask[INTTYPE_SOFTWARE]);
}
void HELPER(intclear)(CPUXtensaState *env, uint32_t v)
{
atomic_and(&env->sregs[INTSET],
~(v & (env->config->inttype_mask[INTTYPE_SOFTWARE] |
env->config->inttype_mask[INTTYPE_EDGE])));
}
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{
if (xtensa_option_enabled(env->config,

2
target/xtensa/helper.c
View File

@ -252,7 +252,7 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
if (runstall) {
cpu_interrupt(cpu, CPU_INTERRUPT_HALT);
} else {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT);
qemu_cpu_kick(cpu);
}
}
#endif

2
target/xtensa/helper.h
View File

@ -22,6 +22,8 @@ DEF_HELPER_1(update_ccount, void, env)
DEF_HELPER_2(wsr_ccount, void, env, i32)
DEF_HELPER_2(update_ccompare, void, env, i32)
DEF_HELPER_1(check_interrupts, void, env)
DEF_HELPER_2(intset, void, env, i32)
DEF_HELPER_2(intclear, void, env, i32)
DEF_HELPER_3(check_atomctl, void, env, i32, i32)
DEF_HELPER_2(wsr_memctl, void, env, i32)

2
target/xtensa/op_helper.c
View File

@ -62,6 +62,8 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
{
uint64_t dcc;
atomic_and(&env->sregs[INTSET],
~(1u << env->config->timerint[i]));
HELPER(update_ccount)(env);
dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
timer_mod(env->ccompare[i].timer,

14
target/xtensa/translate.c
View File

@ -646,20 +646,12 @@ static void gen_check_interrupts(DisasContext *dc)
static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
tcg_gen_andi_i32(cpu_SR[sr], v,
dc->config->inttype_mask[INTTYPE_SOFTWARE]);
gen_helper_intset(cpu_env, v);
}
static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, v,
dc->config->inttype_mask[INTTYPE_EDGE] |
dc->config->inttype_mask[INTTYPE_NMI] |
dc->config->inttype_mask[INTTYPE_SOFTWARE]);
tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
tcg_temp_free(tmp);
gen_helper_intclear(cpu_env, v);
}
static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
@ -706,12 +698,10 @@ static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
uint32_t id = sr - CCOMPARE;
uint32_t int_bit = 1 << dc->config->timerint[id];
TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}