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pci: Trivial device model conversions to realize

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Convert the device models where initialization obviously can't fail.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
This commit is contained in:
Markus Armbruster 2015-01-19 15:52:30 +01:00 committed by Michael S. Tsirkin
parent 7ee6c1e182
commit 9af21dbee1
34 changed files with 87 additions and 152 deletions
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5
hw/acpi/piix4.c
View File

@ -420,7 +420,7 @@ static void piix4_pm_add_propeties(PIIX4PMState *s)
&s->io_base, NULL);
}
static int piix4_pm_initfn(PCIDevice *dev)
static void piix4_pm_realize(PCIDevice *dev, Error **errp)
{
PIIX4PMState *s = PIIX4_PM(dev);
uint8_t *pci_conf;
@ -470,7 +470,6 @@ static int piix4_pm_initfn(PCIDevice *dev)
piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
piix4_pm_add_propeties(s);
return 0;
}
Object *piix4_pm_find(void)
@ -593,7 +592,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
k->init = piix4_pm_initfn;
k->realize = piix4_pm_realize;
k->config_write = pm_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;

5
hw/audio/ac97.c
View File

@ -1337,7 +1337,7 @@ static void ac97_on_reset (DeviceState *dev)
mixer_reset (s);
}
static int ac97_initfn (PCIDevice *dev)
static void ac97_realize(PCIDevice *dev, Error **errp)
{
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
uint8_t *c = s->dev.config;
@ -1384,7 +1384,6 @@ static int ac97_initfn (PCIDevice *dev)
pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
AUD_register_card ("ac97", &s->card);
ac97_on_reset (&s->dev.qdev);
return 0;
}
static int ac97_init (PCIBus *bus)
@ -1403,7 +1402,7 @@ static void ac97_class_init (ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS (klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
k->init = ac97_initfn;
k->realize = ac97_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
k->revision = 0x01;

5
hw/audio/es1370.c
View File

@ -1016,7 +1016,7 @@ static void es1370_on_reset (void *opaque)
es1370_reset (s);
}
static int es1370_initfn (PCIDevice *dev)
static void es1370_realize(PCIDevice *dev, Error **errp)
{
ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
uint8_t *c = s->dev.config;
@ -1039,7 +1039,6 @@ static int es1370_initfn (PCIDevice *dev)
AUD_register_card ("es1370", &s->card);
es1370_reset (s);
return 0;
}
static int es1370_init (PCIBus *bus)
@ -1053,7 +1052,7 @@ static void es1370_class_init (ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS (klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
k->init = es1370_initfn;
k->realize = es1370_realize;
k->vendor_id = PCI_VENDOR_ID_ENSONIQ;
k->device_id = PCI_DEVICE_ID_ENSONIQ_ES1370;
k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;

6
hw/audio/intel-hda.c
View File

@ -1126,7 +1126,7 @@ static void intel_hda_reset(DeviceState *dev)
intel_hda_update_irq(d);
}
static int intel_hda_init(PCIDevice *pci)
static void intel_hda_realize(PCIDevice *pci, Error **errp)
{
IntelHDAState *d = INTEL_HDA(pci);
uint8_t *conf = d->pci.config;
@ -1147,8 +1147,6 @@ static int intel_hda_init(PCIDevice *pci)
hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
intel_hda_response, intel_hda_xfer);
return 0;
}
static void intel_hda_exit(PCIDevice *pci)
@ -1245,7 +1243,7 @@ static void intel_hda_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = intel_hda_init;
k->realize = intel_hda_realize;
k->exit = intel_hda_exit;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;

11
hw/display/vga-pci.c
View File

@ -189,7 +189,7 @@ static const MemoryRegionOps pci_vga_qext_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_std_vga_initfn(PCIDevice *dev)
static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
@ -232,11 +232,9 @@ static int pci_std_vga_initfn(PCIDevice *dev)
/* compatibility with pc-0.13 and older */
vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
}
return 0;
}
static int pci_secondary_vga_initfn(PCIDevice *dev)
static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
@ -268,7 +266,6 @@ static int pci_secondary_vga_initfn(PCIDevice *dev)
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
return 0;
}
static void pci_secondary_vga_reset(DeviceState *dev)
@ -298,7 +295,7 @@ static void vga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_std_vga_initfn;
k->realize = pci_std_vga_realize;
k->romfile = "vgabios-stdvga.bin";
k->vendor_id = PCI_VENDOR_ID_QEMU;
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
@ -314,7 +311,7 @@ static void secondary_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_secondary_vga_initfn;
k->realize = pci_secondary_vga_realize;
k->vendor_id = PCI_VENDOR_ID_QEMU;
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
k->class_id = PCI_CLASS_DISPLAY_OTHER;

6
hw/display/vmware_vga.c
View File

@ -1298,7 +1298,7 @@ static const MemoryRegionOps vmsvga_io_ops = {
},
};
static int pci_vmsvga_initfn(PCIDevice *dev)
static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
{
struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
@ -1323,8 +1323,6 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
/* compatibility with pc-0.13 and older */
vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
}
return 0;
}
static Property vga_vmware_properties[] = {
@ -1338,7 +1336,7 @@ static void vmsvga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_vmsvga_initfn;
k->realize = pci_vmsvga_realize;
k->romfile = "vgabios-vmware.bin";
k->vendor_id = PCI_VENDOR_ID_VMWARE;
k->device_id = SVGA_PCI_DEVICE_ID;

5
hw/i2c/smbus_ich9.c
View File

@ -71,7 +71,7 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
}
}
static int ich9_smbus_initfn(PCIDevice *d)
static void ich9_smbus_realize(PCIDevice *d, Error **errp)
{
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
@ -84,7 +84,6 @@ static int ich9_smbus_initfn(PCIDevice *d)
pm_smbus_init(&d->qdev, &s->smb);
pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&s->smb.io);
return 0;
}
static void ich9_smb_class_init(ObjectClass *klass, void *data)
@ -98,7 +97,7 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_SERIAL_SMBUS;
dc->vmsd = &vmstate_ich9_smbus;
dc->desc = "ICH9 SMBUS Bridge";
k->init = ich9_smbus_initfn;
k->realize = ich9_smbus_realize;
k->config_write = ich9_smbus_write_config;
/*
* Reason: part of ICH9 southbridge, needs to be wired up by

5
hw/ide/cmd646.c
View File

@ -326,7 +326,7 @@ static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
}
/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -374,7 +374,6 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
return 0;
}
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
@ -410,7 +409,7 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_cmd646_ide_initfn;
k->realize = pci_cmd646_ide_realize;
k->exit = pci_cmd646_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_CMD;
k->device_id = PCI_DEVICE_ID_CMD_646;

10
hw/ide/piix.c
View File

@ -148,7 +148,7 @@ static void pci_piix_init_ports(PCIIDEState *d) {
}
}
static int pci_piix_ide_initfn(PCIDevice *dev)
static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -163,8 +163,6 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
pci_piix_init_ports(d);
return 0;
}
int pci_piix3_xen_ide_unplug(DeviceState *dev)
@ -238,7 +236,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
@ -258,7 +256,7 @@ static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
k->class_id = PCI_CLASS_STORAGE_IDE;
@ -276,7 +274,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_piix_ide_initfn;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB;

6
hw/ide/via.c
View File

@ -172,7 +172,7 @@ static void vt82c686b_init_ports(PCIIDEState *d) {
}
/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
@ -187,8 +187,6 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
vt82c686b_init_ports(d);
return 0;
}
static void vt82c686b_ide_exitfn(PCIDevice *dev)
@ -215,7 +213,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_ide_initfn;
k->realize = vt82c686b_ide_realize;
k->exit = vt82c686b_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_IDE;

6
hw/ipack/tpci200.c
View File

@ -573,7 +573,7 @@ static const MemoryRegionOps tpci200_las3_ops = {
}
};
static int tpci200_initfn(PCIDevice *pci_dev)
static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
{
TPCI200State *s = TPCI200(pci_dev);
uint8_t *c = s->dev.config;
@ -609,8 +609,6 @@ static int tpci200_initfn(PCIDevice *pci_dev)
ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
N_MODULES, tpci200_set_irq);
return 0;
}
static const VMStateDescription vmstate_tpci200 = {
@ -632,7 +630,7 @@ static void tpci200_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = tpci200_initfn;
k->realize = tpci200_realize;
k->vendor_id = PCI_VENDOR_ID_TEWS;
k->device_id = PCI_DEVICE_ID_TEWS_TPCI200;
k->class_id = PCI_CLASS_BRIDGE_OTHER;

6
hw/isa/i82378.c
View File

@ -58,7 +58,7 @@ static void i82378_request_pic_irq(void *opaque, int irq, int level)
qemu_set_irq(s->i8259[irq], level);
}
static int i82378_initfn(PCIDevice *pci)
static void i82378_realize(PCIDevice *pci, Error **errp)
{
DeviceState *dev = DEVICE(pci);
I82378State *s = I82378(dev);
@ -107,8 +107,6 @@ static int i82378_initfn(PCIDevice *pci)
/* timer */
isa_create_simple(isabus, "mc146818rtc");
return 0;
}
static void i82378_init(Object *obj)
@ -125,7 +123,7 @@ static void i82378_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = i82378_initfn;
k->realize = i82378_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82378;
k->revision = 0x03;

5
hw/isa/piix4.c
View File

@ -82,7 +82,7 @@ static const VMStateDescription vmstate_piix4 = {
}
};
static int piix4_initfn(PCIDevice *dev)
static void piix4_realize(PCIDevice *dev, Error **errp)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
@ -90,7 +90,6 @@ static int piix4_initfn(PCIDevice *dev)
pci_address_space_io(dev));
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
}
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
@ -107,7 +106,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = piix4_initfn;
k->realize = piix4_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;

24
hw/isa/vt82c686.c
View File

@ -245,7 +245,7 @@ static const VMStateDescription vmstate_acpi = {
* just register a PCI device now, functionalities will be implemented later.
*/
static int vt82c686b_ac97_initfn(PCIDevice *dev)
static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp)
{
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
@ -255,8 +255,6 @@ static int vt82c686b_ac97_initfn(PCIDevice *dev)
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
PCI_STATUS_DEVSEL_MEDIUM);
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
return 0;
}
void vt82c686b_ac97_init(PCIBus *bus, int devfn)
@ -272,7 +270,7 @@ static void via_ac97_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_ac97_initfn;
k->realize = vt82c686b_ac97_realize;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_AC97;
k->revision = 0x50;
@ -288,7 +286,7 @@ static const TypeInfo via_ac97_info = {
.class_init = via_ac97_class_init,
};
static int vt82c686b_mc97_initfn(PCIDevice *dev)
static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp)
{
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
@ -297,8 +295,6 @@ static int vt82c686b_mc97_initfn(PCIDevice *dev)
PCI_COMMAND_VGA_PALETTE);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
return 0;
}
void vt82c686b_mc97_init(PCIBus *bus, int devfn)
@ -314,7 +310,7 @@ static void via_mc97_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_mc97_initfn;
k->realize = vt82c686b_mc97_realize;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_MC97;
k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
@ -331,7 +327,7 @@ static const TypeInfo via_mc97_info = {
};
/* vt82c686 pm init */
static int vt82c686b_pm_initfn(PCIDevice *dev)
static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
{
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
uint8_t *pci_conf;
@ -361,8 +357,6 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
acpi_pm1_cnt_init(&s->ar, &s->io, 2);
return 0;
}
I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@ -391,7 +385,7 @@ static void via_pm_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_pm_initfn;
k->realize = vt82c686b_pm_realize;
k->config_write = pm_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_ACPI;
@ -421,7 +415,7 @@ static const VMStateDescription vmstate_via = {
};
/* init the PCI-to-ISA bridge */
static int vt82c686b_initfn(PCIDevice *d)
static void vt82c686b_realize(PCIDevice *d, Error **errp)
{
VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
uint8_t *pci_conf;
@ -451,8 +445,6 @@ static int vt82c686b_initfn(PCIDevice *d)
&vt82c->superio);
qemu_register_reset(vt82c686b_reset, d);
return 0;
}
ISABus *vt82c686b_init(PCIBus *bus, int devfn)
@ -469,7 +461,7 @@ static void via_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = vt82c686b_initfn;
k->realize = vt82c686b_realize;
k->config_write = vt82c686b_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;

6
hw/misc/pci-testdev.c
View File

@ -233,7 +233,7 @@ static const MemoryRegionOps pci_testdev_pio_ops = {
},
};
static int pci_testdev_init(PCIDevice *pci_dev)
static void pci_testdev_realize(PCIDevice *pci_dev, Error **errp)
{
PCITestDevState *d = PCI_TEST_DEV(pci_dev);
uint8_t *pci_conf;
@ -275,8 +275,6 @@ static int pci_testdev_init(PCIDevice *pci_dev)
assert(r >= 0);
test->hasnotifier = true;
}
return 0;
}
static void
@ -306,7 +304,7 @@ static void pci_testdev_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_testdev_init;
k->realize = pci_testdev_realize;
k->exit = pci_testdev_uninit;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_TEST;

6
hw/net/e1000.c
View File

@ -1537,7 +1537,7 @@ static void e1000_write_config(PCIDevice *pci_dev, uint32_t address,
}
static int pci_e1000_init(PCIDevice *pci_dev)
static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
E1000State *d = E1000(pci_dev);
@ -1581,8 +1581,6 @@ static int pci_e1000_init(PCIDevice *pci_dev)
d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d);
d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d);
return 0;
}
static void qdev_e1000_reset(DeviceState *dev)
@ -1614,7 +1612,7 @@ static void e1000_class_init(ObjectClass *klass, void *data)
E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
const E1000Info *info = data;
k->init = pci_e1000_init;
k->realize = pci_e1000_realize;
k->exit = pci_e1000_uninit;
k->romfile = "efi-e1000.rom";
k->vendor_id = PCI_VENDOR_ID_INTEL;

6
hw/net/eepro100.c
View File

@ -1848,7 +1848,7 @@ static NetClientInfo net_eepro100_info = {
.receive = nic_receive,
};
static int e100_nic_init(PCIDevice *pci_dev)
static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
E100PCIDeviceInfo *info = eepro100_get_class(s);
@ -1892,8 +1892,6 @@ static int e100_nic_init(PCIDevice *pci_dev)
memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
s->vmstate->name = qemu_get_queue(s->nic)->model;
vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
return 0;
}
static void eepro100_instance_init(Object *obj)
@ -2083,7 +2081,7 @@ static void eepro100_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
k->romfile = "pxe-eepro100.rom";
k->init = e100_nic_init;
k->realize = e100_nic_realize;
k->exit = pci_nic_uninit;
k->device_id = info->device_id;
k->revision = info->revision;

6
hw/net/ne2000.c
View File

@ -709,7 +709,7 @@ static NetClientInfo net_ne2000_info = {
.receive = ne2000_receive,
};
static int pci_ne2000_init(PCIDevice *pci_dev)
static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s;
@ -729,8 +729,6 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
return 0;
}
static void pci_ne2000_exit(PCIDevice *pci_dev)
@ -763,7 +761,7 @@ static void ne2000_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_ne2000_init;
k->realize = pci_ne2000_realize;
k->exit = pci_ne2000_exit;
k->romfile = "efi-ne2k_pci.rom",
k->vendor_id = PCI_VENDOR_ID_REALTEK;

6
hw/net/rtl8139.c
View File

@ -3455,7 +3455,7 @@ static NetClientInfo net_rtl8139_info = {
.link_status_changed = rtl8139_set_link_status,
};
static int pci_rtl8139_init(PCIDevice *dev)
static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
{
RTL8139State *s = RTL8139(dev);
DeviceState *d = DEVICE(dev);
@ -3496,8 +3496,6 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->cplus_txbuffer_offset = 0;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
return 0;
}
static void rtl8139_instance_init(Object *obj)
@ -3519,7 +3517,7 @@ static void rtl8139_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_rtl8139_init;
k->realize = pci_rtl8139_realize;
k->exit = pci_rtl8139_uninit;
k->romfile = "efi-rtl8139.rom";
k->vendor_id = PCI_VENDOR_ID_REALTEK;

6
hw/net/vmxnet3.c
View File

@ -2125,7 +2125,7 @@ static const MemoryRegionOps b1_ops = {
},
};
static int vmxnet3_pci_init(PCIDevice *pci_dev)
static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
@ -2164,8 +2164,6 @@ static int vmxnet3_pci_init(PCIDevice *pci_dev)
register_savevm(dev, "vmxnet3-msix", -1, 1,
vmxnet3_msix_save, vmxnet3_msix_load, s);
return 0;
}
static void vmxnet3_instance_init(Object *obj)
@ -2501,7 +2499,7 @@ static void vmxnet3_class_init(ObjectClass *class, void *data)
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
c->init = vmxnet3_pci_init;
c->realize = vmxnet3_pci_realize;
c->exit = vmxnet3_pci_uninit;
c->vendor_id = PCI_VENDOR_ID_VMWARE;
c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;

5
hw/pci-bridge/dec.c
View File

@ -107,10 +107,9 @@ static int pci_dec_21154_device_init(SysBusDevice *dev)
return 0;
}
static int dec_21154_pci_host_init(PCIDevice *d)
static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp)
{
/* PCI2PCI bridge same values as PearPC - check this */
return 0;
}
static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
@ -118,7 +117,7 @@ static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = dec_21154_pci_host_init;
k->realize = dec_21154_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_DEC;
k->device_id = PCI_DEVICE_ID_DEC_21154;
k->revision = 0x02;

5
hw/pci-host/apb.c
View File

@ -792,14 +792,13 @@ static int pci_pbm_init_device(SysBusDevice *dev)
return 0;
}
static int pbm_pci_host_init(PCIDevice *d)
static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
return 0;
}
static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
@ -807,7 +806,7 @@ static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = pbm_pci_host_init;
k->realize = pbm_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_SUN;
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
k->class_id = PCI_CLASS_BRIDGE_HOST;

6
hw/pci-host/bonito.c
View File

@ -705,7 +705,7 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
return 0;
}
static int bonito_initfn(PCIDevice *dev)
static void bonito_realize(PCIDevice *dev, Error **errp)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
@ -766,8 +766,6 @@ static int bonito_initfn(PCIDevice *dev)
pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
qemu_register_reset(bonito_reset, s);
return 0;
}
PCIBus *bonito_init(qemu_irq *pic)
@ -799,7 +797,7 @@ static void bonito_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = bonito_initfn;
k->realize = bonito_realize;
k->vendor_id = 0xdf53;
k->device_id = 0x00d5;
k->revision = 0x01;

5
hw/pci-host/grackle.c
View File

@ -114,10 +114,9 @@ static int pci_grackle_init_device(SysBusDevice *dev)
return 0;
}
static int grackle_pci_host_init(PCIDevice *d)
static void grackle_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x09] = 0x01;
return 0;
}
static void grackle_pci_class_init(ObjectClass *klass, void *data)
@ -125,7 +124,7 @@ static void grackle_pci_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = grackle_pci_host_init;
k->realize = grackle_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
k->revision = 0x00;

12
hw/pci-host/piix.c
View File

@ -295,14 +295,13 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
sysbus_init_ioports(sbd, 0xcfc, 4);
}
static int i440fx_initfn(PCIDevice *dev)
static void i440fx_realize(PCIDevice *dev, Error **errp)
{
PCII440FXState *d = I440FX_PCI_DEVICE(dev);
dev->config[I440FX_SMRAM] = 0x02;
cpu_smm_register(&i440fx_set_smm, d);
return 0;
}
PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
@ -631,7 +630,7 @@ static const MemoryRegionOps rcr_ops = {
.endianness = DEVICE_LITTLE_ENDIAN
};
static int piix3_initfn(PCIDevice *dev)
static void piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
@ -644,7 +643,6 @@ static int piix3_initfn(PCIDevice *dev)
&d->rcr_mem, 1);
qemu_register_reset(piix3_reset, d);
return 0;
}
static void piix3_class_init(ObjectClass *klass, void *data)
@ -655,7 +653,7 @@ static void piix3_class_init(ObjectClass *klass, void *data)
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->init = piix3_initfn;
k->realize = piix3_realize;
k->config_write = piix3_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
@ -683,7 +681,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data)
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->init = piix3_initfn;
k->realize = piix3_realize;
k->config_write = piix3_write_config_xen;
k->vendor_id = PCI_VENDOR_ID_INTEL;
/* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
@ -708,7 +706,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = i440fx_initfn;
k->realize = i440fx_realize;
k->config_write = i440fx_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82441;

6
hw/pci-host/ppce500.c
View File

@ -416,7 +416,7 @@ static const VMStateDescription vmstate_ppce500_pci = {
#include "exec/address-spaces.h"
static int e500_pcihost_bridge_initfn(PCIDevice *d)
static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
{
PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
@ -430,8 +430,6 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d)
memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
0, int128_get64(ccsr->ccsr_space.size));
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
return 0;
}
static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
@ -500,7 +498,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = e500_pcihost_bridge_initfn;
k->realize = e500_pcihost_bridge_realize;
k->vendor_id = PCI_VENDOR_ID_FREESCALE;
k->device_id = PCI_DEVICE_ID_MPC8533E;
k->class_id = PCI_CLASS_PROCESSOR_POWERPC;

6
hw/pci-host/prep.c
View File

@ -289,7 +289,7 @@ static void raven_pcihost_initfn(Object *obj)
qdev_prop_set_bit(pci_dev, "multifunction", false);
}
static int raven_init(PCIDevice *d)
static void raven_realize(PCIDevice *d, Error **errp)
{
RavenPCIState *s = RAVEN_PCI_DEVICE(d);
char *filename;
@ -330,8 +330,6 @@ static int raven_init(PCIDevice *d)
g_free(filename);
}
}
return 0;
}
static const VMStateDescription vmstate_raven = {
@ -349,7 +347,7 @@ static void raven_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = raven_init;
k->realize = raven_realize;
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
k->revision = 0x00;

5
hw/pci-host/q35.c
View File

@ -390,7 +390,7 @@ static void mch_init_dmar(MCHPCIState *mch)
pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
}
static int mch_init(PCIDevice *d)
static void mch_realize(PCIDevice *d, Error **errp)
{
int i;
MCHPCIState *mch = MCH_PCI_DEVICE(d);
@ -418,7 +418,6 @@ static int mch_init(PCIDevice *d)
if (qemu_opt_get_bool(qemu_get_machine_opts(), "iommu", false)) {
mch_init_dmar(mch);
}
return 0;
}
uint64_t mch_mcfg_base(void)
@ -436,7 +435,7 @@ static void mch_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = mch_init;
k->realize = mch_realize;
k->config_write = mch_write_config;
dc->reset = mch_reset;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

20
hw/pci-host/uninorth.c
View File

@ -315,37 +315,33 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
return h->bus;
}
static int unin_main_pci_host_init(PCIDevice *d)
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
return 0;
}
static int unin_agp_pci_host_init(PCIDevice *d)
static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
// d->config[0x34] = 0x80; // capabilities_pointer
return 0;
}
static int u3_agp_pci_host_init(PCIDevice *d)
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
/* cache line size */
d->config[0x0C] = 0x08;
/* latency timer */
d->config[0x0D] = 0x10;
return 0;
}
static int unin_internal_pci_host_init(PCIDevice *d)
static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
return 0;
}
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
@ -353,7 +349,7 @@ static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_main_pci_host_init;
k->realize = unin_main_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
k->revision = 0x00;
@ -377,7 +373,7 @@ static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = u3_agp_pci_host_init;
k->realize = u3_agp_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
k->revision = 0x00;
@ -401,7 +397,7 @@ static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_agp_pci_host_init;
k->realize = unin_agp_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
k->revision = 0x00;
@ -425,7 +421,7 @@ static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = unin_internal_pci_host_init;
k->realize = unin_internal_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
k->revision = 0x00;

5
hw/pci-host/versatile.c
View File

@ -456,12 +456,11 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
}
static int versatile_pci_host_init(PCIDevice *d)
static void versatile_pci_host_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
return 0;
}
static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
@ -469,7 +468,7 @@ static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->init = versatile_pci_host_init;
k->realize = versatile_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_XILINX;
k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
k->class_id = PCI_CLASS_PROCESSOR_CO;

5
hw/sd/sdhci.c
View File

@ -1220,7 +1220,7 @@ static Property sdhci_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static int sdhci_pci_init(PCIDevice *dev)
static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
{
SDHCIState *s = PCI_SDHCI(dev);
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
@ -1232,7 +1232,6 @@ static int sdhci_pci_init(PCIDevice *dev)
memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
SDHC_REGISTERS_MAP_SIZE);
pci_register_bar(dev, 0, 0, &s->iomem);
return 0;
}
static void sdhci_pci_exit(PCIDevice *dev)
@ -1246,7 +1245,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = sdhci_pci_init;
k->realize = sdhci_pci_realize;
k->exit = sdhci_pci_exit;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;

6
hw/usb/hcd-ehci-pci.c
View File

@ -26,7 +26,7 @@ typedef struct EHCIPCIInfo {
bool companion;
} EHCIPCIInfo;
static int usb_ehci_pci_initfn(PCIDevice *dev)
static void usb_ehci_pci_realize(PCIDevice *dev, Error **errp)
{
EHCIPCIState *i = PCI_EHCI(dev);
EHCIState *s = &i->ehci;
@ -66,8 +66,6 @@ static int usb_ehci_pci_initfn(PCIDevice *dev)
usb_ehci_realize(s, DEVICE(dev), NULL);
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
return 0;
}
static void usb_ehci_pci_init(Object *obj)
@ -139,7 +137,7 @@ static void ehci_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = usb_ehci_pci_initfn;
k->realize = usb_ehci_pci_realize;
k->exit = usb_ehci_pci_exit;
k->class_id = PCI_CLASS_SERIAL_USB;
k->config_write = usb_ehci_pci_write_config;

6
hw/usb/hcd-xhci.c
View File

@ -3567,7 +3567,7 @@ static void usb_xhci_init(XHCIState *xhci)
}
}
static int usb_xhci_initfn(struct PCIDevice *dev)
static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
{
int i, ret;
@ -3646,8 +3646,6 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
&xhci->mem, 0, OFF_MSIX_PBA,
0x90);
}
return 0;
}
static void usb_xhci_exit(PCIDevice *dev)
@ -3887,7 +3885,7 @@ static void xhci_class_init(ObjectClass *klass, void *data)
dc->props = xhci_properties;
dc->reset = xhci_reset;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
k->init = usb_xhci_initfn;
k->realize = usb_xhci_realize;
k->exit = usb_xhci_exit;
k->vendor_id = PCI_VENDOR_ID_NEC;
k->device_id = PCI_DEVICE_ID_NEC_UPD720200;

6
hw/watchdog/wdt_i6300esb.c
View File

@ -408,7 +408,7 @@ static const VMStateDescription vmstate_i6300esb = {
}
};
static int i6300esb_init(PCIDevice *dev)
static void i6300esb_realize(PCIDevice *dev, Error **errp)
{
I6300State *d = DO_UPCAST(I6300State, dev, dev);
@ -421,8 +421,6 @@ static int i6300esb_init(PCIDevice *dev)
"i6300esb", 0x10);
pci_register_bar(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
return 0;
}
static WatchdogTimerModel model = {
@ -437,7 +435,7 @@ static void i6300esb_class_init(ObjectClass *klass, void *data)
k->config_read = i6300esb_config_read;
k->config_write = i6300esb_config_write;
k->init = i6300esb_init;
k->realize = i6300esb_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
k->class_id = PCI_CLASS_SYSTEM_OTHER;