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target/xtensa: Convert to TranslatorOps
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Richard Henderson
Max Filippov
parent
1d38a7011f
commit
9c509ff94e
@ -1055,148 +1055,163 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
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}
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}
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
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CPUState *cpu)
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{
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CPUXtensaState *env = cs->env_ptr;
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DisasContext dc1, *dc = &dc1;
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int insn_count = 0;
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int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
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uint32_t pc_start = tb->pc;
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uint32_t page_start = pc_start & TARGET_PAGE_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUXtensaState *env = cpu->env_ptr;
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uint32_t tb_flags = dc->base.tb->flags;
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dc->config = env->config;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->base.tb = tb;
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dc->pc = pc_start;
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dc->ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
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dc->cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
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dc->pc = dc->base.pc_first;
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dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
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dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
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dc->lbeg = env->sregs[LBEG];
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dc->lend = env->sregs[LEND];
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dc->base.is_jmp = DISAS_NEXT;
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dc->debug = tb->flags & XTENSA_TBFLAG_DEBUG;
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dc->icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
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dc->cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
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dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
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dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
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dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
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XTENSA_TBFLAG_CPENABLE_SHIFT;
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dc->window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
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dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
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XTENSA_TBFLAG_WINDOW_SHIFT);
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if (dc->config->isa) {
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dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
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dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
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}
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init_sar_tracker(dc);
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}
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static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (dc->icount) {
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dc->next_icount = tcg_temp_local_new_i32();
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}
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}
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gen_tb_start(tb);
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static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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tcg_gen_insn_start(dcbase->pc_next);
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}
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if ((tb_cflags(tb) & CF_USE_ICOUNT) &&
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(tb->flags & XTENSA_TBFLAG_YIELD)) {
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tcg_gen_insn_start(dc->pc);
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++insn_count;
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static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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const CPUBreakpoint *bp)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
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gen_exception(dc, EXCP_DEBUG);
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dc->base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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dc->base.pc_next += 2;
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return true;
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}
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static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUXtensaState *env = cpu->env_ptr;
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target_ulong page_start;
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/* These two conditions only apply to the first insn in the TB,
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but this is the first TranslateOps hook that allows exiting. */
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if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
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&& (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
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gen_exception(dc, EXCP_YIELD);
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dc->base.is_jmp = DISAS_NORETURN;
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goto done;
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return;
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}
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if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
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tcg_gen_insn_start(dc->pc);
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++insn_count;
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if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) {
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gen_exception(dc, EXCP_DEBUG);
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dc->base.is_jmp = DISAS_NORETURN;
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goto done;
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return;
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}
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do {
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tcg_gen_insn_start(dc->pc);
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++insn_count;
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if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_exception(dc, EXCP_DEBUG);
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dc->base.is_jmp = DISAS_NORETURN;
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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dc->pc += 2;
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break;
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}
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if (insn_count == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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}
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if (dc->icount) {
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TCGLabel *label = gen_new_label();
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tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
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tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
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tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
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if (dc->debug) {
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gen_debug_exception(dc, DEBUGCAUSE_IC);
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}
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gen_set_label(label);
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}
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if (dc->debug) {
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gen_ibreak_check(env, dc);
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}
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disas_xtensa_insn(env, dc);
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if (dc->icount) {
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tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
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}
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if (dc->base.singlestep_enabled) {
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_exception(dc, EXCP_DEBUG);
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break;
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}
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} while (dc->base.is_jmp == DISAS_NEXT &&
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insn_count < max_insns &&
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dc->pc - page_start < TARGET_PAGE_SIZE &&
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dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE
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&& !tcg_op_buf_full());
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done:
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reset_sar_tracker(dc);
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if (dc->icount) {
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tcg_temp_free(dc->next_icount);
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TCGLabel *label = gen_new_label();
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tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
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tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
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tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
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if (dc->debug) {
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gen_debug_exception(dc, DEBUGCAUSE_IC);
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}
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gen_set_label(label);
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}
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if (dc->debug) {
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gen_ibreak_check(env, dc);
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}
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disas_xtensa_insn(env, dc);
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if (dc->icount) {
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tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
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}
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/* End the TB if the next insn will cross into the next page. */
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page_start = dc->base.pc_first & TARGET_PAGE_MASK;
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if (dc->base.is_jmp == DISAS_NEXT &&
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(dc->pc - page_start >= TARGET_PAGE_SIZE ||
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dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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reset_sar_tracker(dc);
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if (dc->config->isa) {
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xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
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xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
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}
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if (tb_cflags(tb) & CF_LAST_IO) {
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gen_io_end();
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if (dc->icount) {
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tcg_temp_free(dc->next_icount);
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}
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if (dc->base.is_jmp == DISAS_NEXT) {
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gen_jumpi(dc, dc->pc, 0);
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switch (dc->base.is_jmp) {
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case DISAS_NORETURN:
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break;
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case DISAS_TOO_MANY:
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if (dc->base.singlestep_enabled) {
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_exception(dc, EXCP_DEBUG);
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} else {
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gen_jumpi(dc, dc->pc, 0);
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}
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break;
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default:
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g_assert_not_reached();
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}
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gen_tb_end(tb, insn_count);
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}
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(pc_start)) {
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qemu_log_lock();
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qemu_log("----------------\n");
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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log_target_disas(cs, pc_start, dc->pc - pc_start);
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qemu_log("\n");
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qemu_log_unlock();
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}
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#endif
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tb->size = dc->pc - pc_start;
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tb->icount = insn_count;
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static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
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{
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qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
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log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
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}
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static const TranslatorOps xtensa_translator_ops = {
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.init_disas_context = xtensa_tr_init_disas_context,
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.tb_start = xtensa_tr_tb_start,
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.insn_start = xtensa_tr_insn_start,
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.breakpoint_check = xtensa_tr_breakpoint_check,
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.translate_insn = xtensa_tr_translate_insn,
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.tb_stop = xtensa_tr_tb_stop,
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.disas_log = xtensa_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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{
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DisasContext dc = {};
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translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
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}
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void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
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