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target/arm: Handle trapping to EL2 of AArch32 VMRS instructions

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HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.

Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-4-maz@kernel.org
[PMM: move helper declaration to helper.h; make it
 TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Marc Zyngier 2019-12-01 12:20:16 +00:00 committed by Peter Maydell
parent 93fbc983b2
commit 9ca1d776cb
3 changed files with 47 additions and 4 deletions
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2
target/arm/helper.h
View File

@ -226,6 +226,8 @@ DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
/* neon_helper.c */
DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)

20
target/arm/translate-vfp.inc.c
View File

@ -761,13 +761,25 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
if (a->l) {
/* VMRS, move VFP special register to gp register */
switch (a->reg) {
case ARM_VFP_FPSID:
case ARM_VFP_FPEXC:
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
case ARM_VFP_FPSID:
if (s->current_el == 1) {
TCGv_i32 tcg_reg, tcg_rt;
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_reg = tcg_const_i32(a->reg);
tcg_rt = tcg_const_i32(a->rt);
gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg);
tcg_temp_free_i32(tcg_reg);
tcg_temp_free_i32(tcg_rt);
}
/* fall through */
case ARM_VFP_FPEXC:
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
tmp = load_cpu_field(vfp.xregs[a->reg]);
break;
case ARM_VFP_FPSCR:

29
target/arm/vfp_helper.c
View File

@ -1322,4 +1322,33 @@ float64 HELPER(frint64_d)(float64 f, void *fpst)
return frint_d(f, fpst, 64);
}
void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
{
uint32_t syndrome;
switch (reg) {
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
return;
}
break;
case ARM_VFP_FPSID:
if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
return;
}
break;
default:
g_assert_not_reached();
}
syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
| ARM_EL_IL
| (1 << 24) | (0xe << 20) | (7 << 14)
| (reg << 10) | (rt << 5) | 1);
raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
}
#endif