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target/avr: Add instruction translation - Branch Instructions

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This includes:
    - RJMP, IJMP, EIJMP, JMP
    - RCALL, ICALL, EICALL, CALL
    - RET, RETI
    - CPSE, CP, CPC, CPI
    - SBRC, SBRS, SBIC, SBIS
    - BRBC, BRBS

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-13-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-24 01:51:11 +01:00 committed by Philippe Mathieu-Daudé
parent 865f3bb9e1
commit 9d316c75ab
2 changed files with 576 additions and 0 deletions
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33
target/avr/insn.decode
View File

@ -74,3 +74,36 @@ FMUL 0000 0011 0 ... 1 ... @fmul
FMULS 0000 0011 1 ... 0 ... @fmul
FMULSU 0000 0011 1 ... 1 ... @fmul
DES 1001 0100 imm:4 1011
#
# Branch Instructions
#
# The 22-bit immediate is partially in the opcode word,
# and partially in the next. Use append_16 to build the
# complete 22-bit value.
%imm_call 4:5 0:1 !function=append_16
@op_bit .... .... . bit:3 ....
@op_bit_imm .... .. imm:s7 bit:3
RJMP 1100 imm:s12
IJMP 1001 0100 0000 1001
EIJMP 1001 0100 0001 1001
JMP 1001 010 ..... 110 . imm=%imm_call
RCALL 1101 imm:s12
ICALL 1001 0101 0000 1001
EICALL 1001 0101 0001 1001
CALL 1001 010 ..... 111 . imm=%imm_call
RET 1001 0101 0000 1000
RETI 1001 0101 0001 1000
CPSE 0001 00 . ..... .... @op_rd_rr
CP 0001 01 . ..... .... @op_rd_rr
CPC 0000 01 . ..... .... @op_rd_rr
CPI 0011 .... .... .... @op_rd_imm8
SBRC 1111 110 rr:5 0 bit:3
SBRS 1111 111 rr:5 0 bit:3
SBIC 1001 1001 reg:5 bit:3
SBIS 1001 1011 reg:5 bit:3
BRBS 1111 00 ....... ... @op_bit_imm
BRBC 1111 01 ....... ... @op_bit_imm

543
target/avr/translate.c
View File

@ -144,6 +144,16 @@ static int to_regs_24_30_by_two(DisasContext *ctx, int indx)
}
static uint16_t next_word(DisasContext *ctx)
{
return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
}
static int append_16(DisasContext *ctx, int x)
{
return x << 16 | next_word(ctx);
}
static bool avr_have_feature(DisasContext *ctx, int feature)
{
if (!avr_feature(ctx->env, feature)) {
@ -960,3 +970,536 @@ static bool trans_DES(DisasContext *ctx, arg_DES *a)
return true;
}
/*
* Branch Instructions
*/
static void gen_jmp_ez(DisasContext *ctx)
{
tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind);
ctx->bstate = DISAS_LOOKUP;
}
static void gen_jmp_z(DisasContext *ctx)
{
tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8);
ctx->bstate = DISAS_LOOKUP;
}
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x0000ff));
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_temp_free_i32(t0);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x00ffff));
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_temp_free_i32(t0);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo = tcg_const_i32((ret & 0x0000ff));
TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_temp_free_i32(lo);
tcg_temp_free_i32(hi);
}
}
static void gen_pop_ret(DisasContext *ctx, TCGv ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo = tcg_temp_new_i32();
TCGv hi = tcg_temp_new_i32();
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
tcg_temp_free_i32(lo);
tcg_temp_free_i32(hi);
}
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb = ctx->tb;
if (ctx->singlestep == 0) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb(tb, n);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
gen_helper_debug(cpu_env);
tcg_gen_exit_tb(NULL, 0);
}
ctx->bstate = DISAS_NORETURN;
}
/*
* Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
* AVR microcontrollers with Program memory not exceeding 4K words (8KB) this
* instruction can address the entire memory from every address location. See
* also JMP.
*/
static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a)
{
int dst = ctx->npc + a->imm;
gen_goto_tb(ctx, 0, dst);
return true;
}
/*
* Indirect jump to the address pointed to by the Z (16 bits) Pointer
* Register in the Register File. The Z-pointer Register is 16 bits wide and
* allows jump within the lowest 64K words (128KB) section of Program memory.
* This instruction is not available in all devices. Refer to the device
* specific instruction set summary.
*/
static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
return true;
}
gen_jmp_z(ctx);
return true;
}
/*
* Indirect jump to the address pointed to by the Z (16 bits) Pointer
* Register in the Register File and the EIND Register in the I/O space. This
* instruction allows for indirect jumps to the entire 4M (words) Program
* memory space. See also IJMP. This instruction is not available in all
* devices. Refer to the device specific instruction set summary.
*/
static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
return true;
}
gen_jmp_ez(ctx);
return true;
}
/*
* Jump to an address within the entire 4M (words) Program memory. See also
* RJMP. This instruction is not available in all devices. Refer to the device
* specific instruction set summary.0
*/
static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
return true;
}
gen_goto_tb(ctx, 0, a->imm);
return true;
}
/*
* Relative call to an address within PC - 2K + 1 and PC + 2K (words). The
* return address (the instruction after the RCALL) is stored onto the Stack.
* See also CALL. For AVR microcontrollers with Program memory not exceeding 4K
* words (8KB) this instruction can address the entire memory from every
* address location. The Stack Pointer uses a post-decrement scheme during
* RCALL.
*/
static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a)
{
int ret = ctx->npc;
int dst = ctx->npc + a->imm;
gen_push_ret(ctx, ret);
gen_goto_tb(ctx, 0, dst);
return true;
}
/*
* Calls to a subroutine within the entire 4M (words) Program memory. The
* return address (to the instruction after the CALL) will be stored onto the
* Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
* CALL. This instruction is not available in all devices. Refer to the device
* specific instruction set summary.
*/
static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) {
return true;
}
int ret = ctx->npc;
gen_push_ret(ctx, ret);
gen_jmp_z(ctx);
return true;
}
/*
* Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
* Register in the Register File and the EIND Register in the I/O space. This
* instruction allows for indirect calls to the entire 4M (words) Program
* memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
* during EICALL. This instruction is not available in all devices. Refer to
* the device specific instruction set summary.
*/
static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) {
return true;
}
int ret = ctx->npc;
gen_push_ret(ctx, ret);
gen_jmp_ez(ctx);
return true;
}
/*
* Calls to a subroutine within the entire Program memory. The return
* address (to the instruction after the CALL) will be stored onto the Stack.
* (See also RCALL). The Stack Pointer uses a post-decrement scheme during
* CALL. This instruction is not available in all devices. Refer to the device
* specific instruction set summary.
*/
static bool trans_CALL(DisasContext *ctx, arg_CALL *a)
{
if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) {
return true;
}
int Imm = a->imm;
int ret = ctx->npc;
gen_push_ret(ctx, ret);
gen_goto_tb(ctx, 0, Imm);
return true;
}
/*
* Returns from subroutine. The return address is loaded from the STACK.
* The Stack Pointer uses a preincrement scheme during RET.
*/
static bool trans_RET(DisasContext *ctx, arg_RET *a)
{
gen_pop_ret(ctx, cpu_pc);
ctx->bstate = DISAS_LOOKUP;
return true;
}
/*
* Returns from interrupt. The return address is loaded from the STACK and
* the Global Interrupt Flag is set. Note that the Status Register is not
* automatically stored when entering an interrupt routine, and it is not
* restored when returning from an interrupt routine. This must be handled by
* the application program. The Stack Pointer uses a pre-increment scheme
* during RETI.
*/
static bool trans_RETI(DisasContext *ctx, arg_RETI *a)
{
gen_pop_ret(ctx, cpu_pc);
tcg_gen_movi_tl(cpu_If, 1);
/* Need to return to main loop to re-evaluate interrupts. */
ctx->bstate = DISAS_EXIT;
return true;
}
/*
* This instruction performs a compare between two registers Rd and Rr, and
* skips the next instruction if Rd = Rr.
*/
static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a)
{
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = cpu_r[a->rd];
ctx->skip_var1 = cpu_r[a->rr];
return true;
}
/*
* This instruction performs a compare between two registers Rd and Rr.
* None of the registers are changed. All conditional branches can be used
* after this instruction.
*/
static bool trans_CP(DisasContext *ctx, arg_CP *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
/* update status register */
gen_sub_CHf(R, Rd, Rr);
gen_sub_Vf(R, Rd, Rr);
gen_ZNSf(R);
tcg_temp_free_i32(R);
return true;
}
/*
* This instruction performs a compare between two registers Rd and Rr and
* also takes into account the previous carry. None of the registers are
* changed. All conditional branches can be used after this instruction.
*/
static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
/* update status register */
gen_sub_CHf(R, Rd, Rr);
gen_sub_Vf(R, Rd, Rr);
gen_NSf(R);
/*
* Previous value remains unchanged when the result is zero;
* cleared otherwise.
*/
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero);
tcg_temp_free_i32(zero);
tcg_temp_free_i32(R);
return true;
}
/*
* This instruction performs a compare between register Rd and a constant.
* The register is not changed. All conditional branches can be used after this
* instruction.
*/
static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
TCGv Rr = tcg_const_i32(Imm);
TCGv R = tcg_temp_new_i32();
tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
/* update status register */
gen_sub_CHf(R, Rd, Rr);
gen_sub_Vf(R, Rd, Rr);
gen_ZNSf(R);
tcg_temp_free_i32(R);
tcg_temp_free_i32(Rr);
return true;
}
/*
* This instruction tests a single bit in a register and skips the next
* instruction if the bit is cleared.
*/
static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
{
TCGv Rr = cpu_r[a->rr];
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
return true;
}
/*
* This instruction tests a single bit in a register and skips the next
* instruction if the bit is set.
*/
static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
{
TCGv Rr = cpu_r[a->rr];
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit);
return true;
}
/*
* This instruction tests a single bit in an I/O Register and skips the
* next instruction if the bit is cleared. This instruction operates on the
* lower 32 I/O Registers -- addresses 0-31.
*/
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
{
TCGv temp = tcg_const_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = temp;
ctx->free_skip_var0 = true;
return true;
}
/*
* This instruction tests a single bit in an I/O Register and skips the
* next instruction if the bit is set. This instruction operates on the lower
* 32 I/O Registers -- addresses 0-31.
*/
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
{
TCGv temp = tcg_const_i32(a->reg);
gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = temp;
ctx->free_skip_var0 = true;
return true;
}
/*
* Conditional relative branch. Tests a single bit in SREG and branches
* relatively to PC if the bit is cleared. This instruction branches relatively
* to PC in either direction (PC - 63 < = destination <= PC + 64). The
* parameter k is the offset from PC and is represented in two's complement
* form.
*/
static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a)
{
TCGLabel *not_taken = gen_new_label();
TCGv var;
switch (a->bit) {
case 0x00:
var = cpu_Cf;
break;
case 0x01:
var = cpu_Zf;
break;
case 0x02:
var = cpu_Nf;
break;
case 0x03:
var = cpu_Vf;
break;
case 0x04:
var = cpu_Sf;
break;
case 0x05:
var = cpu_Hf;
break;
case 0x06:
var = cpu_Tf;
break;
case 0x07:
var = cpu_If;
break;
default:
g_assert_not_reached();
}
tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken);
gen_goto_tb(ctx, 0, ctx->npc + a->imm);
gen_set_label(not_taken);
ctx->bstate = DISAS_CHAIN;
return true;
}
/*
* Conditional relative branch. Tests a single bit in SREG and branches
* relatively to PC if the bit is set. This instruction branches relatively to
* PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
* is the offset from PC and is represented in two's complement form.
*/
static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a)
{
TCGLabel *not_taken = gen_new_label();
TCGv var;
switch (a->bit) {
case 0x00:
var = cpu_Cf;
break;
case 0x01:
var = cpu_Zf;
break;
case 0x02:
var = cpu_Nf;
break;
case 0x03:
var = cpu_Vf;
break;
case 0x04:
var = cpu_Sf;
break;
case 0x05:
var = cpu_Hf;
break;
case 0x06:
var = cpu_Tf;
break;
case 0x07:
var = cpu_If;
break;
default:
g_assert_not_reached();
}
tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken);
gen_goto_tb(ctx, 0, ctx->npc + a->imm);
gen_set_label(not_taken);
ctx->bstate = DISAS_CHAIN;
return true;
}