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riscv: sifive: Implement a model for SiFive FU540 OTP
This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng
Palmer Dabbelt
parent
6c141fb7dd
commit
9fb45c62ae
@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
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obj-$(CONFIG_SIFIVE) += sifive_plic.o
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obj-$(CONFIG_SIFIVE) += sifive_plic.o
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obj-$(CONFIG_SIFIVE) += sifive_test.o
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obj-$(CONFIG_SIFIVE) += sifive_test.o
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obj-$(CONFIG_SIFIVE_U) += sifive_u.o
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obj-$(CONFIG_SIFIVE_U) += sifive_u.o
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obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o
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obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
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obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
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obj-$(CONFIG_SIFIVE) += sifive_uart.o
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obj-$(CONFIG_SIFIVE) += sifive_uart.o
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obj-$(CONFIG_SPIKE) += spike.o
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obj-$(CONFIG_SPIKE) += spike.o
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191
hw/riscv/sifive_u_otp.c
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191
hw/riscv/sifive_u_otp.c
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@ -0,0 +1,191 @@
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/*
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* QEMU SiFive U OTP (One-Time Programmable) Memory interface
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*
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* Simple model of the OTP to emulate register reads made by the SDK BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/riscv/sifive_u_otp.h"
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static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
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{
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SiFiveUOTPState *s = opaque;
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switch (addr) {
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case SIFIVE_U_OTP_PA:
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return s->pa;
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case SIFIVE_U_OTP_PAIO:
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return s->paio;
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case SIFIVE_U_OTP_PAS:
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return s->pas;
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case SIFIVE_U_OTP_PCE:
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return s->pce;
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case SIFIVE_U_OTP_PCLK:
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return s->pclk;
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case SIFIVE_U_OTP_PDIN:
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return s->pdin;
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case SIFIVE_U_OTP_PDOUT:
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if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
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(s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
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(s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
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return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
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} else {
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return 0xff;
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}
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case SIFIVE_U_OTP_PDSTB:
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return s->pdstb;
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case SIFIVE_U_OTP_PPROG:
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return s->pprog;
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case SIFIVE_U_OTP_PTC:
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return s->ptc;
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case SIFIVE_U_OTP_PTM:
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return s->ptm;
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case SIFIVE_U_OTP_PTM_REP:
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return s->ptm_rep;
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case SIFIVE_U_OTP_PTR:
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return s->ptr;
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case SIFIVE_U_OTP_PTRIM:
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return s->ptrim;
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case SIFIVE_U_OTP_PWE:
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return s->pwe;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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static void sifive_u_otp_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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SiFiveUOTPState *s = opaque;
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uint32_t val32 = (uint32_t)val64;
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switch (addr) {
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case SIFIVE_U_OTP_PA:
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s->pa = val32 & SIFIVE_U_OTP_PA_MASK;
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break;
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case SIFIVE_U_OTP_PAIO:
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s->paio = val32;
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break;
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case SIFIVE_U_OTP_PAS:
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s->pas = val32;
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break;
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case SIFIVE_U_OTP_PCE:
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s->pce = val32;
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break;
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case SIFIVE_U_OTP_PCLK:
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s->pclk = val32;
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break;
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case SIFIVE_U_OTP_PDIN:
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s->pdin = val32;
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break;
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case SIFIVE_U_OTP_PDOUT:
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/* read-only */
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break;
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case SIFIVE_U_OTP_PDSTB:
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s->pdstb = val32;
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break;
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case SIFIVE_U_OTP_PPROG:
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s->pprog = val32;
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break;
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case SIFIVE_U_OTP_PTC:
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s->ptc = val32;
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break;
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case SIFIVE_U_OTP_PTM:
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s->ptm = val32;
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break;
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case SIFIVE_U_OTP_PTM_REP:
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s->ptm_rep = val32;
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break;
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case SIFIVE_U_OTP_PTR:
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s->ptr = val32;
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break;
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case SIFIVE_U_OTP_PTRIM:
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s->ptrim = val32;
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break;
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case SIFIVE_U_OTP_PWE:
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s->pwe = val32;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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" v=0x%x\n", __func__, addr, val32);
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}
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}
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static const MemoryRegionOps sifive_u_otp_ops = {
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.read = sifive_u_otp_read,
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.write = sifive_u_otp_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static Property sifive_u_otp_properties[] = {
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DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
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{
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SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
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memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
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TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
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}
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static void sifive_u_otp_reset(DeviceState *dev)
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{
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SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
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/* Initialize all fuses' initial value to 0xFFs */
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memset(s->fuse, 0xff, sizeof(s->fuse));
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/* Make a valid content of serial number */
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s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
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s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
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}
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static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = sifive_u_otp_properties;
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dc->realize = sifive_u_otp_realize;
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dc->reset = sifive_u_otp_reset;
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}
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static const TypeInfo sifive_u_otp_info = {
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.name = TYPE_SIFIVE_U_OTP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFiveUOTPState),
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.class_init = sifive_u_otp_class_init,
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};
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static void sifive_u_otp_register_types(void)
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{
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type_register_static(&sifive_u_otp_info);
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}
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type_init(sifive_u_otp_register_types)
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80
include/hw/riscv/sifive_u_otp.h
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80
include/hw/riscv/sifive_u_otp.h
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@ -0,0 +1,80 @@
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/*
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* QEMU SiFive U OTP (One-Time Programmable) Memory interface
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*
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_U_OTP_H
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#define HW_SIFIVE_U_OTP_H
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#define SIFIVE_U_OTP_PA 0x00
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#define SIFIVE_U_OTP_PAIO 0x04
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#define SIFIVE_U_OTP_PAS 0x08
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#define SIFIVE_U_OTP_PCE 0x0C
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#define SIFIVE_U_OTP_PCLK 0x10
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#define SIFIVE_U_OTP_PDIN 0x14
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#define SIFIVE_U_OTP_PDOUT 0x18
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#define SIFIVE_U_OTP_PDSTB 0x1C
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#define SIFIVE_U_OTP_PPROG 0x20
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#define SIFIVE_U_OTP_PTC 0x24
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#define SIFIVE_U_OTP_PTM 0x28
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#define SIFIVE_U_OTP_PTM_REP 0x2C
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#define SIFIVE_U_OTP_PTR 0x30
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#define SIFIVE_U_OTP_PTRIM 0x34
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#define SIFIVE_U_OTP_PWE 0x38
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#define SIFIVE_U_OTP_PCE_EN (1 << 0)
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#define SIFIVE_U_OTP_PDSTB_EN (1 << 0)
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#define SIFIVE_U_OTP_PTRIM_EN (1 << 0)
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#define SIFIVE_U_OTP_PA_MASK 0xfff
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#define SIFIVE_U_OTP_NUM_FUSES 0x1000
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#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc
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#define SIFIVE_U_OTP_REG_SIZE 0x1000
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#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp"
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#define SIFIVE_U_OTP(obj) \
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OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
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typedef struct SiFiveUOTPState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t pa;
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uint32_t paio;
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uint32_t pas;
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uint32_t pce;
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uint32_t pclk;
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uint32_t pdin;
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uint32_t pdstb;
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uint32_t pprog;
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uint32_t ptc;
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uint32_t ptm;
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uint32_t ptm_rep;
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uint32_t ptr;
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uint32_t ptrim;
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uint32_t pwe;
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uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
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/* config */
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uint32_t serial;
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} SiFiveUOTPState;
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#endif /* HW_SIFIVE_U_OTP_H */
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