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escc: remove register changes from escc_reset_chn()

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Now that register values at reset are handled elsewhere for all of device reset,
soft reset and hard reset, escc_reset_chn() only needs to handle initialisation
of internal device state.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Mark Cave-Ayland 2021-09-03 12:32:21 +01:00
parent 160509aebe
commit a04ca92a54
1 changed files with 0 additions and 25 deletions
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25
hw/char/escc.c
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@ -139,7 +139,6 @@
#define MISC2_PLLCMD0 0x20
#define MISC2_PLLCMD1 0x40
#define MISC2_PLLCMD2 0x80
#define MISC2_PLLDIS 0x30
#define W_EXTINT 15
#define EXTINT_DCD 0x08
#define EXTINT_SYNCINT 0x10
@ -279,31 +278,7 @@ static void escc_update_irq(ESCCChannelState *s)
static void escc_reset_chn(ESCCChannelState *s)
{
int i;
s->reg = 0;
for (i = 0; i < ESCC_SERIAL_REGS; i++) {
s->rregs[i] = 0;
s->wregs[i] = 0;
}
/* 1X divisor, 1 stop bit, no parity */
s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
s->wregs[W_MINTR] = MINTR_RST_ALL;
/* Synch mode tx clock = TRxC */
s->wregs[W_CLOCK] = CLOCK_TRXC;
/* PLL disabled */
s->wregs[W_MISC2] = MISC2_PLLDIS;
/* Enable most interrupts */
s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
EXTINT_TXUNDRN | EXTINT_BRKINT;
if (s->disabled) {
s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
STATUS_CTS | STATUS_TXUNDRN;
} else {
s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
}
s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
s->rx = s->tx = 0;
s->rxint = s->txint = 0;
s->rxint_under_svc = s->txint_under_svc = 0;