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hw/display: fix tab indentation

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The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370
Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com>
Message-Id: <5cefd05b4d3721d416e48e6df19df18cb6338933.1666707782.git.amarjargal16@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Amarjargal Gundjalam 2022-10-25 22:28:10 +08:00 committed by Thomas Huth
parent ef99aa2a31
commit a076a3dcbf
6 changed files with 1499 additions and 1499 deletions
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352
hw/display/blizzard.c
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@ -123,14 +123,14 @@ typedef struct {
/* Bytes(!) per pixel */
static const int blizzard_iformat_bpp[0x10] = {
0,
2, /* RGB 5:6:5*/
3, /* RGB 6:6:6 mode 1 */
3, /* RGB 8:8:8 mode 1 */
2, /* RGB 5:6:5*/
3, /* RGB 6:6:6 mode 1 */
3, /* RGB 8:8:8 mode 1 */
0, 0,
4, /* RGB 6:6:6 mode 2 */
4, /* RGB 8:8:8 mode 2 */
0, /* YUV 4:2:2 */
0, /* YUV 4:2:0 */
4, /* RGB 6:6:6 mode 2 */
4, /* RGB 8:8:8 mode 2 */
0, /* YUV 4:2:2 */
0, /* YUV 4:2:0 */
0, 0, 0, 0, 0, 0,
};
@ -281,196 +281,196 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
BlizzardState *s = (BlizzardState *) opaque;
switch (reg) {
case 0x00: /* Revision Code */
case 0x00: /* Revision Code */
return 0xa5;
case 0x02: /* Configuration Readback */
return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
case 0x02: /* Configuration Readback */
return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
case 0x04: /* PLL M-Divider */
case 0x04: /* PLL M-Divider */
return (s->pll - 1) | (1 << 7);
case 0x06: /* PLL Lock Range Control */
case 0x06: /* PLL Lock Range Control */
return s->pll_range;
case 0x08: /* PLL Lock Synthesis Control 0 */
case 0x08: /* PLL Lock Synthesis Control 0 */
return s->pll_ctrl & 0xff;
case 0x0a: /* PLL Lock Synthesis Control 1 */
case 0x0a: /* PLL Lock Synthesis Control 1 */
return s->pll_ctrl >> 8;
case 0x0c: /* PLL Mode Control 0 */
case 0x0c: /* PLL Mode Control 0 */
return s->pll_mode;
case 0x0e: /* Clock-Source Select */
case 0x0e: /* Clock-Source Select */
return s->clksel;
case 0x10: /* Memory Controller Activate */
case 0x14: /* Memory Controller Bank 0 Status Flag */
case 0x10: /* Memory Controller Activate */
case 0x14: /* Memory Controller Bank 0 Status Flag */
return s->memenable;
case 0x18: /* Auto-Refresh Interval Setting 0 */
case 0x18: /* Auto-Refresh Interval Setting 0 */
return s->memrefresh & 0xff;
case 0x1a: /* Auto-Refresh Interval Setting 1 */
case 0x1a: /* Auto-Refresh Interval Setting 1 */
return s->memrefresh >> 8;
case 0x1c: /* Power-On Sequence Timing Control */
case 0x1c: /* Power-On Sequence Timing Control */
return s->timing[0];
case 0x1e: /* Timing Control 0 */
case 0x1e: /* Timing Control 0 */
return s->timing[1];
case 0x20: /* Timing Control 1 */
case 0x20: /* Timing Control 1 */
return s->timing[2];
case 0x24: /* Arbitration Priority Control */
case 0x24: /* Arbitration Priority Control */
return s->priority;
case 0x28: /* LCD Panel Configuration */
case 0x28: /* LCD Panel Configuration */
return s->lcd_config;
case 0x2a: /* LCD Horizontal Display Width */
case 0x2a: /* LCD Horizontal Display Width */
return s->x >> 3;
case 0x2c: /* LCD Horizontal Non-display Period */
case 0x2c: /* LCD Horizontal Non-display Period */
return s->hndp;
case 0x2e: /* LCD Vertical Display Height 0 */
case 0x2e: /* LCD Vertical Display Height 0 */
return s->y & 0xff;
case 0x30: /* LCD Vertical Display Height 1 */
case 0x30: /* LCD Vertical Display Height 1 */
return s->y >> 8;
case 0x32: /* LCD Vertical Non-display Period */
case 0x32: /* LCD Vertical Non-display Period */
return s->vndp;
case 0x34: /* LCD HS Pulse-width */
case 0x34: /* LCD HS Pulse-width */
return s->hsync;
case 0x36: /* LCd HS Pulse Start Position */
case 0x36: /* LCd HS Pulse Start Position */
return s->skipx >> 3;
case 0x38: /* LCD VS Pulse-width */
case 0x38: /* LCD VS Pulse-width */
return s->vsync;
case 0x3a: /* LCD VS Pulse Start Position */
case 0x3a: /* LCD VS Pulse Start Position */
return s->skipy;
case 0x3c: /* PCLK Polarity */
case 0x3c: /* PCLK Polarity */
return s->pclk;
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
return s->hssi_config[0];
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
return s->hssi_config[1];
case 0x42: /* High-speed Serial Interface Tx Mode */
case 0x42: /* High-speed Serial Interface Tx Mode */
return s->hssi_config[2];
case 0x44: /* TV Display Configuration */
case 0x44: /* TV Display Configuration */
return s->tv_config;
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
return s->tv_timing[(reg - 0x46) >> 1];
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
return s->vbi;
case 0x50: /* TV Horizontal Start Position */
case 0x50: /* TV Horizontal Start Position */
return s->tv_x;
case 0x52: /* TV Vertical Start Position */
case 0x52: /* TV Vertical Start Position */
return s->tv_y;
case 0x54: /* TV Test Pattern Setting */
case 0x54: /* TV Test Pattern Setting */
return s->tv_test;
case 0x56: /* TV Filter Setting */
case 0x56: /* TV Filter Setting */
return s->tv_filter_config;
case 0x58: /* TV Filter Coefficient Index */
case 0x58: /* TV Filter Coefficient Index */
return s->tv_filter_idx;
case 0x5a: /* TV Filter Coefficient Data */
case 0x5a: /* TV Filter Coefficient Data */
if (s->tv_filter_idx < 0x20)
return s->tv_filter_coeff[s->tv_filter_idx ++];
return 0;
case 0x60: /* Input YUV/RGB Translate Mode 0 */
case 0x60: /* Input YUV/RGB Translate Mode 0 */
return s->yrc[0];
case 0x62: /* Input YUV/RGB Translate Mode 1 */
case 0x62: /* Input YUV/RGB Translate Mode 1 */
return s->yrc[1];
case 0x64: /* U Data Fix */
case 0x64: /* U Data Fix */
return s->u;
case 0x66: /* V Data Fix */
case 0x66: /* V Data Fix */
return s->v;
case 0x68: /* Display Mode */
case 0x68: /* Display Mode */
return s->mode;
case 0x6a: /* Special Effects */
case 0x6a: /* Special Effects */
return s->effect;
case 0x6c: /* Input Window X Start Position 0 */
case 0x6c: /* Input Window X Start Position 0 */
return s->ix[0] & 0xff;
case 0x6e: /* Input Window X Start Position 1 */
case 0x6e: /* Input Window X Start Position 1 */
return s->ix[0] >> 3;
case 0x70: /* Input Window Y Start Position 0 */
case 0x70: /* Input Window Y Start Position 0 */
return s->ix[0] & 0xff;
case 0x72: /* Input Window Y Start Position 1 */
case 0x72: /* Input Window Y Start Position 1 */
return s->ix[0] >> 3;
case 0x74: /* Input Window X End Position 0 */
case 0x74: /* Input Window X End Position 0 */
return s->ix[1] & 0xff;
case 0x76: /* Input Window X End Position 1 */
case 0x76: /* Input Window X End Position 1 */
return s->ix[1] >> 3;
case 0x78: /* Input Window Y End Position 0 */
case 0x78: /* Input Window Y End Position 0 */
return s->ix[1] & 0xff;
case 0x7a: /* Input Window Y End Position 1 */
case 0x7a: /* Input Window Y End Position 1 */
return s->ix[1] >> 3;
case 0x7c: /* Output Window X Start Position 0 */
case 0x7c: /* Output Window X Start Position 0 */
return s->ox[0] & 0xff;
case 0x7e: /* Output Window X Start Position 1 */
case 0x7e: /* Output Window X Start Position 1 */
return s->ox[0] >> 3;
case 0x80: /* Output Window Y Start Position 0 */
case 0x80: /* Output Window Y Start Position 0 */
return s->oy[0] & 0xff;
case 0x82: /* Output Window Y Start Position 1 */
case 0x82: /* Output Window Y Start Position 1 */
return s->oy[0] >> 3;
case 0x84: /* Output Window X End Position 0 */
case 0x84: /* Output Window X End Position 0 */
return s->ox[1] & 0xff;
case 0x86: /* Output Window X End Position 1 */
case 0x86: /* Output Window X End Position 1 */
return s->ox[1] >> 3;
case 0x88: /* Output Window Y End Position 0 */
case 0x88: /* Output Window Y End Position 0 */
return s->oy[1] & 0xff;
case 0x8a: /* Output Window Y End Position 1 */
case 0x8a: /* Output Window Y End Position 1 */
return s->oy[1] >> 3;
case 0x8c: /* Input Data Format */
case 0x8c: /* Input Data Format */
return s->iformat;
case 0x8e: /* Data Source Select */
case 0x8e: /* Data Source Select */
return s->source;
case 0x90: /* Display Memory Data Port */
case 0x90: /* Display Memory Data Port */
return 0;
case 0xa8: /* Border Color 0 */
case 0xa8: /* Border Color 0 */
return s->border_r;
case 0xaa: /* Border Color 1 */
case 0xaa: /* Border Color 1 */
return s->border_g;
case 0xac: /* Border Color 2 */
case 0xac: /* Border Color 2 */
return s->border_b;
case 0xb4: /* Gamma Correction Enable */
case 0xb4: /* Gamma Correction Enable */
return s->gamma_config;
case 0xb6: /* Gamma Correction Table Index */
case 0xb6: /* Gamma Correction Table Index */
return s->gamma_idx;
case 0xb8: /* Gamma Correction Table Data */
case 0xb8: /* Gamma Correction Table Data */
return s->gamma_lut[s->gamma_idx ++];
case 0xba: /* 3x3 Matrix Enable */
case 0xba: /* 3x3 Matrix Enable */
return s->matrix_ena;
case 0xbc ... 0xde: /* Coefficient Registers */
case 0xbc ... 0xde: /* Coefficient Registers */
return s->matrix_coeff[(reg - 0xbc) >> 1];
case 0xe0: /* 3x3 Matrix Red Offset */
case 0xe0: /* 3x3 Matrix Red Offset */
return s->matrix_r;
case 0xe2: /* 3x3 Matrix Green Offset */
case 0xe2: /* 3x3 Matrix Green Offset */
return s->matrix_g;
case 0xe4: /* 3x3 Matrix Blue Offset */
case 0xe4: /* 3x3 Matrix Blue Offset */
return s->matrix_b;
case 0xe6: /* Power-save */
case 0xe6: /* Power-save */
return s->pm;
case 0xe8: /* Non-display Period Control / Status */
case 0xe8: /* Non-display Period Control / Status */
return s->status | (1 << 5);
case 0xea: /* RGB Interface Control */
case 0xea: /* RGB Interface Control */
return s->rgbgpio_dir;
case 0xec: /* RGB Interface Status */
case 0xec: /* RGB Interface Status */
return s->rgbgpio;
case 0xee: /* General-purpose IO Pins Configuration */
case 0xee: /* General-purpose IO Pins Configuration */
return s->gpio_dir;
case 0xf0: /* General-purpose IO Pins Status / Control */
case 0xf0: /* General-purpose IO Pins Status / Control */
return s->gpio;
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
return s->gpio_edge[0];
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
return s->gpio_edge[1];
case 0xf6: /* GPIO Interrupt Status */
case 0xf6: /* GPIO Interrupt Status */
return s->gpio_irq;
case 0xf8: /* GPIO Pull-down Control */
case 0xf8: /* GPIO Pull-down Control */
return s->gpio_pdown;
default:
@ -484,157 +484,157 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
BlizzardState *s = (BlizzardState *) opaque;
switch (reg) {
case 0x04: /* PLL M-Divider */
case 0x04: /* PLL M-Divider */
s->pll = (value & 0x3f) + 1;
break;
case 0x06: /* PLL Lock Range Control */
case 0x06: /* PLL Lock Range Control */
s->pll_range = value & 3;
break;
case 0x08: /* PLL Lock Synthesis Control 0 */
case 0x08: /* PLL Lock Synthesis Control 0 */
s->pll_ctrl &= 0xf00;
s->pll_ctrl |= (value << 0) & 0x0ff;
break;
case 0x0a: /* PLL Lock Synthesis Control 1 */
case 0x0a: /* PLL Lock Synthesis Control 1 */
s->pll_ctrl &= 0x0ff;
s->pll_ctrl |= (value << 8) & 0xf00;
break;
case 0x0c: /* PLL Mode Control 0 */
case 0x0c: /* PLL Mode Control 0 */
s->pll_mode = value & 0x77;
if ((value & 3) == 0 || (value & 3) == 3)
fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
__func__, value & 3);
break;
case 0x0e: /* Clock-Source Select */
case 0x0e: /* Clock-Source Select */
s->clksel = value & 0xff;
break;
case 0x10: /* Memory Controller Activate */
case 0x10: /* Memory Controller Activate */
s->memenable = value & 1;
break;
case 0x14: /* Memory Controller Bank 0 Status Flag */
case 0x14: /* Memory Controller Bank 0 Status Flag */
break;
case 0x18: /* Auto-Refresh Interval Setting 0 */
case 0x18: /* Auto-Refresh Interval Setting 0 */
s->memrefresh &= 0xf00;
s->memrefresh |= (value << 0) & 0x0ff;
break;
case 0x1a: /* Auto-Refresh Interval Setting 1 */
case 0x1a: /* Auto-Refresh Interval Setting 1 */
s->memrefresh &= 0x0ff;
s->memrefresh |= (value << 8) & 0xf00;
break;
case 0x1c: /* Power-On Sequence Timing Control */
case 0x1c: /* Power-On Sequence Timing Control */
s->timing[0] = value & 0x7f;
break;
case 0x1e: /* Timing Control 0 */
case 0x1e: /* Timing Control 0 */
s->timing[1] = value & 0x17;
break;
case 0x20: /* Timing Control 1 */
case 0x20: /* Timing Control 1 */
s->timing[2] = value & 0x35;
break;
case 0x24: /* Arbitration Priority Control */
case 0x24: /* Arbitration Priority Control */
s->priority = value & 1;
break;
case 0x28: /* LCD Panel Configuration */
case 0x28: /* LCD Panel Configuration */
s->lcd_config = value & 0xff;
if (value & (1 << 7))
fprintf(stderr, "%s: data swap not supported!\n", __func__);
break;
case 0x2a: /* LCD Horizontal Display Width */
case 0x2a: /* LCD Horizontal Display Width */
s->x = value << 3;
break;
case 0x2c: /* LCD Horizontal Non-display Period */
case 0x2c: /* LCD Horizontal Non-display Period */
s->hndp = value & 0xff;
break;
case 0x2e: /* LCD Vertical Display Height 0 */
case 0x2e: /* LCD Vertical Display Height 0 */
s->y &= 0x300;
s->y |= (value << 0) & 0x0ff;
break;
case 0x30: /* LCD Vertical Display Height 1 */
case 0x30: /* LCD Vertical Display Height 1 */
s->y &= 0x0ff;
s->y |= (value << 8) & 0x300;
break;
case 0x32: /* LCD Vertical Non-display Period */
case 0x32: /* LCD Vertical Non-display Period */
s->vndp = value & 0xff;
break;
case 0x34: /* LCD HS Pulse-width */
case 0x34: /* LCD HS Pulse-width */
s->hsync = value & 0xff;
break;
case 0x36: /* LCD HS Pulse Start Position */
case 0x36: /* LCD HS Pulse Start Position */
s->skipx = value & 0xff;
break;
case 0x38: /* LCD VS Pulse-width */
case 0x38: /* LCD VS Pulse-width */
s->vsync = value & 0xbf;
break;
case 0x3a: /* LCD VS Pulse Start Position */
case 0x3a: /* LCD VS Pulse Start Position */
s->skipy = value & 0xff;
break;
case 0x3c: /* PCLK Polarity */
case 0x3c: /* PCLK Polarity */
s->pclk = value & 0x82;
/* Affects calculation of s->hndp, s->hsync and s->skipx. */
break;
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
s->hssi_config[0] = value;
break;
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
s->hssi_config[1] = value;
if (((value >> 4) & 3) == 3)
fprintf(stderr, "%s: Illegal active-data-links value\n",
__func__);
break;
case 0x42: /* High-speed Serial Interface Tx Mode */
case 0x42: /* High-speed Serial Interface Tx Mode */
s->hssi_config[2] = value & 0xbd;
break;
case 0x44: /* TV Display Configuration */
case 0x44: /* TV Display Configuration */
s->tv_config = value & 0xfe;
break;
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
s->tv_timing[(reg - 0x46) >> 1] = value;
break;
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
s->vbi = value;
break;
case 0x50: /* TV Horizontal Start Position */
case 0x50: /* TV Horizontal Start Position */
s->tv_x = value;
break;
case 0x52: /* TV Vertical Start Position */
case 0x52: /* TV Vertical Start Position */
s->tv_y = value & 0x7f;
break;
case 0x54: /* TV Test Pattern Setting */
case 0x54: /* TV Test Pattern Setting */
s->tv_test = value;
break;
case 0x56: /* TV Filter Setting */
case 0x56: /* TV Filter Setting */
s->tv_filter_config = value & 0xbf;
break;
case 0x58: /* TV Filter Coefficient Index */
case 0x58: /* TV Filter Coefficient Index */
s->tv_filter_idx = value & 0x1f;
break;
case 0x5a: /* TV Filter Coefficient Data */
case 0x5a: /* TV Filter Coefficient Data */
if (s->tv_filter_idx < 0x20)
s->tv_filter_coeff[s->tv_filter_idx ++] = value;
break;
case 0x60: /* Input YUV/RGB Translate Mode 0 */
case 0x60: /* Input YUV/RGB Translate Mode 0 */
s->yrc[0] = value & 0xb0;
break;
case 0x62: /* Input YUV/RGB Translate Mode 1 */
case 0x62: /* Input YUV/RGB Translate Mode 1 */
s->yrc[1] = value & 0x30;
break;
case 0x64: /* U Data Fix */
case 0x64: /* U Data Fix */
s->u = value & 0xff;
break;
case 0x66: /* V Data Fix */
case 0x66: /* V Data Fix */
s->v = value & 0xff;
break;
case 0x68: /* Display Mode */
case 0x68: /* Display Mode */
if ((s->mode ^ value) & 3)
s->invalidate = 1;
s->mode = value & 0xb7;
@ -644,83 +644,83 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
fprintf(stderr, "%s: Macrovision enable attempt!\n", __func__);
break;
case 0x6a: /* Special Effects */
case 0x6a: /* Special Effects */
s->effect = value & 0xfb;
break;
case 0x6c: /* Input Window X Start Position 0 */
case 0x6c: /* Input Window X Start Position 0 */
s->ix[0] &= 0x300;
s->ix[0] |= (value << 0) & 0x0ff;
break;
case 0x6e: /* Input Window X Start Position 1 */
case 0x6e: /* Input Window X Start Position 1 */
s->ix[0] &= 0x0ff;
s->ix[0] |= (value << 8) & 0x300;
break;
case 0x70: /* Input Window Y Start Position 0 */
case 0x70: /* Input Window Y Start Position 0 */
s->iy[0] &= 0x300;
s->iy[0] |= (value << 0) & 0x0ff;
break;
case 0x72: /* Input Window Y Start Position 1 */
case 0x72: /* Input Window Y Start Position 1 */
s->iy[0] &= 0x0ff;
s->iy[0] |= (value << 8) & 0x300;
break;
case 0x74: /* Input Window X End Position 0 */
case 0x74: /* Input Window X End Position 0 */
s->ix[1] &= 0x300;
s->ix[1] |= (value << 0) & 0x0ff;
break;
case 0x76: /* Input Window X End Position 1 */
case 0x76: /* Input Window X End Position 1 */
s->ix[1] &= 0x0ff;
s->ix[1] |= (value << 8) & 0x300;
break;
case 0x78: /* Input Window Y End Position 0 */
case 0x78: /* Input Window Y End Position 0 */
s->iy[1] &= 0x300;
s->iy[1] |= (value << 0) & 0x0ff;
break;
case 0x7a: /* Input Window Y End Position 1 */
case 0x7a: /* Input Window Y End Position 1 */
s->iy[1] &= 0x0ff;
s->iy[1] |= (value << 8) & 0x300;
break;
case 0x7c: /* Output Window X Start Position 0 */
case 0x7c: /* Output Window X Start Position 0 */
s->ox[0] &= 0x300;
s->ox[0] |= (value << 0) & 0x0ff;
break;
case 0x7e: /* Output Window X Start Position 1 */
case 0x7e: /* Output Window X Start Position 1 */
s->ox[0] &= 0x0ff;
s->ox[0] |= (value << 8) & 0x300;
break;
case 0x80: /* Output Window Y Start Position 0 */
case 0x80: /* Output Window Y Start Position 0 */
s->oy[0] &= 0x300;
s->oy[0] |= (value << 0) & 0x0ff;
break;
case 0x82: /* Output Window Y Start Position 1 */
case 0x82: /* Output Window Y Start Position 1 */
s->oy[0] &= 0x0ff;
s->oy[0] |= (value << 8) & 0x300;
break;
case 0x84: /* Output Window X End Position 0 */
case 0x84: /* Output Window X End Position 0 */
s->ox[1] &= 0x300;
s->ox[1] |= (value << 0) & 0x0ff;
break;
case 0x86: /* Output Window X End Position 1 */
case 0x86: /* Output Window X End Position 1 */
s->ox[1] &= 0x0ff;
s->ox[1] |= (value << 8) & 0x300;
break;
case 0x88: /* Output Window Y End Position 0 */
case 0x88: /* Output Window Y End Position 0 */
s->oy[1] &= 0x300;
s->oy[1] |= (value << 0) & 0x0ff;
break;
case 0x8a: /* Output Window Y End Position 1 */
case 0x8a: /* Output Window Y End Position 1 */
s->oy[1] &= 0x0ff;
s->oy[1] |= (value << 8) & 0x300;
break;
case 0x8c: /* Input Data Format */
case 0x8c: /* Input Data Format */
s->iformat = value & 0xf;
s->bpp = blizzard_iformat_bpp[s->iformat];
if (!s->bpp)
fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
__func__, s->iformat);
break;
case 0x8e: /* Data Source Select */
case 0x8e: /* Data Source Select */
s->source = value & 7;
/* Currently all windows will be "destructive overlays". */
if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
@ -735,7 +735,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
blizzard_transfer_setup(s);
break;
case 0x90: /* Display Memory Data Port */
case 0x90: /* Display Memory Data Port */
if (!s->data.len && !blizzard_transfer_setup(s))
break;
@ -744,73 +744,73 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
blizzard_window(s);
break;
case 0xa8: /* Border Color 0 */
case 0xa8: /* Border Color 0 */
s->border_r = value;
break;
case 0xaa: /* Border Color 1 */
case 0xaa: /* Border Color 1 */
s->border_g = value;
break;
case 0xac: /* Border Color 2 */
case 0xac: /* Border Color 2 */
s->border_b = value;
break;
case 0xb4: /* Gamma Correction Enable */
case 0xb4: /* Gamma Correction Enable */
s->gamma_config = value & 0x87;
break;
case 0xb6: /* Gamma Correction Table Index */
case 0xb6: /* Gamma Correction Table Index */
s->gamma_idx = value;
break;
case 0xb8: /* Gamma Correction Table Data */
case 0xb8: /* Gamma Correction Table Data */
s->gamma_lut[s->gamma_idx ++] = value;
break;
case 0xba: /* 3x3 Matrix Enable */
case 0xba: /* 3x3 Matrix Enable */
s->matrix_ena = value & 1;
break;
case 0xbc ... 0xde: /* Coefficient Registers */
case 0xbc ... 0xde: /* Coefficient Registers */
s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
break;
case 0xe0: /* 3x3 Matrix Red Offset */
case 0xe0: /* 3x3 Matrix Red Offset */
s->matrix_r = value;
break;
case 0xe2: /* 3x3 Matrix Green Offset */
case 0xe2: /* 3x3 Matrix Green Offset */
s->matrix_g = value;
break;
case 0xe4: /* 3x3 Matrix Blue Offset */
case 0xe4: /* 3x3 Matrix Blue Offset */
s->matrix_b = value;
break;
case 0xe6: /* Power-save */
case 0xe6: /* Power-save */
s->pm = value & 0x83;
if (value & s->mode & 1)
fprintf(stderr, "%s: The display must be disabled before entering "
"Standby Mode\n", __func__);
break;
case 0xe8: /* Non-display Period Control / Status */
case 0xe8: /* Non-display Period Control / Status */
s->status = value & 0x1b;
break;
case 0xea: /* RGB Interface Control */
case 0xea: /* RGB Interface Control */
s->rgbgpio_dir = value & 0x8f;
break;
case 0xec: /* RGB Interface Status */
case 0xec: /* RGB Interface Status */
s->rgbgpio = value & 0xcf;
break;
case 0xee: /* General-purpose IO Pins Configuration */
case 0xee: /* General-purpose IO Pins Configuration */
s->gpio_dir = value;
break;
case 0xf0: /* General-purpose IO Pins Status / Control */
case 0xf0: /* General-purpose IO Pins Status / Control */
s->gpio = value;
break;
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
s->gpio_edge[0] = value;
break;
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
s->gpio_edge[1] = value;
break;
case 0xf6: /* GPIO Interrupt Status */
case 0xf6: /* GPIO Interrupt Status */
s->gpio_irq &= value;
break;
case 0xf8: /* GPIO Pull-down Control */
case 0xf8: /* GPIO Pull-down Control */
s->gpio_pdown = value;
break;

1600
hw/display/cirrus_vga.c
View File

File diff suppressed because it is too large Load Diff

598
hw/display/omap_dss.c
View File

@ -182,25 +182,25 @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x00: /* DSS_REVISIONNUMBER */
return 0x20;
case 0x10: /* DSS_SYSCONFIG */
case 0x10: /* DSS_SYSCONFIG */
return s->autoidle;
case 0x14: /* DSS_SYSSTATUS */
return 1; /* RESETDONE */
case 0x14: /* DSS_SYSSTATUS */
return 1; /* RESETDONE */
case 0x40: /* DSS_CONTROL */
case 0x40: /* DSS_CONTROL */
return s->control;
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
/* TODO: fake some values when appropriate s->control bits are set */
return 0;
case 0x5c: /* DSS_STATUS */
case 0x5c: /* DSS_STATUS */
return 1 + (s->control & 1);
default:
@ -221,22 +221,22 @@ static void omap_diss_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x5c: /* DSS_STATUS */
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x5c: /* DSS_STATUS */
OMAP_RO_REG(addr);
break;
case 0x10: /* DSS_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x10: /* DSS_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dss_reset(s);
s->autoidle = value & 1;
break;
case 0x40: /* DSS_CONTROL */
case 0x40: /* DSS_CONTROL */
s->control = value & 0x3dd;
break;
@ -261,112 +261,112 @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x000: /* DISPC_REVISION */
case 0x000: /* DISPC_REVISION */
return 0x20;
case 0x010: /* DISPC_SYSCONFIG */
case 0x010: /* DISPC_SYSCONFIG */
return s->dispc.idlemode;
case 0x014: /* DISPC_SYSSTATUS */
return 1; /* RESETDONE */
case 0x014: /* DISPC_SYSSTATUS */
return 1; /* RESETDONE */
case 0x018: /* DISPC_IRQSTATUS */
case 0x018: /* DISPC_IRQSTATUS */
return s->dispc.irqst;
case 0x01c: /* DISPC_IRQENABLE */
case 0x01c: /* DISPC_IRQENABLE */
return s->dispc.irqen;
case 0x040: /* DISPC_CONTROL */
case 0x040: /* DISPC_CONTROL */
return s->dispc.control;
case 0x044: /* DISPC_CONFIG */
case 0x044: /* DISPC_CONFIG */
return s->dispc.config;
case 0x048: /* DISPC_CAPABLE */
case 0x048: /* DISPC_CAPABLE */
return s->dispc.capable;
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
return s->dispc.bg[0];
case 0x050: /* DISPC_DEFAULT_COLOR1 */
case 0x050: /* DISPC_DEFAULT_COLOR1 */
return s->dispc.bg[1];
case 0x054: /* DISPC_TRANS_COLOR0 */
case 0x054: /* DISPC_TRANS_COLOR0 */
return s->dispc.trans[0];
case 0x058: /* DISPC_TRANS_COLOR1 */
case 0x058: /* DISPC_TRANS_COLOR1 */
return s->dispc.trans[1];
case 0x05c: /* DISPC_LINE_STATUS */
case 0x05c: /* DISPC_LINE_STATUS */
return 0x7ff;
case 0x060: /* DISPC_LINE_NUMBER */
case 0x060: /* DISPC_LINE_NUMBER */
return s->dispc.line;
case 0x064: /* DISPC_TIMING_H */
case 0x064: /* DISPC_TIMING_H */
return s->dispc.timing[0];
case 0x068: /* DISPC_TIMING_V */
case 0x068: /* DISPC_TIMING_V */
return s->dispc.timing[1];
case 0x06c: /* DISPC_POL_FREQ */
case 0x06c: /* DISPC_POL_FREQ */
return s->dispc.timing[2];
case 0x070: /* DISPC_DIVISOR */
case 0x070: /* DISPC_DIVISOR */
return s->dispc.timing[3];
case 0x078: /* DISPC_SIZE_DIG */
case 0x078: /* DISPC_SIZE_DIG */
return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);
case 0x07c: /* DISPC_SIZE_LCD */
case 0x07c: /* DISPC_SIZE_LCD */
return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);
case 0x080: /* DISPC_GFX_BA0 */
case 0x080: /* DISPC_GFX_BA0 */
return s->dispc.l[0].addr[0];
case 0x084: /* DISPC_GFX_BA1 */
case 0x084: /* DISPC_GFX_BA1 */
return s->dispc.l[0].addr[1];
case 0x088: /* DISPC_GFX_POSITION */
case 0x088: /* DISPC_GFX_POSITION */
return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;
case 0x08c: /* DISPC_GFX_SIZE */
case 0x08c: /* DISPC_GFX_SIZE */
return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
return s->dispc.l[0].attr;
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
return s->dispc.l[0].tresh;
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
return 256;
case 0x0ac: /* DISPC_GFX_ROW_INC */
case 0x0ac: /* DISPC_GFX_ROW_INC */
return s->dispc.l[0].rowinc;
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
return s->dispc.l[0].colinc;
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
return s->dispc.l[0].wininc;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
case 0x0b8: /* DISPC_GFX_TABLE_BA */
return s->dispc.l[0].addr[2];
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
return 0;
default:
@ -387,33 +387,33 @@ static void omap_disc_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dss_reset(s);
s->dispc.idlemode = value & 0x301b;
break;
case 0x018: /* DISPC_IRQSTATUS */
case 0x018: /* DISPC_IRQSTATUS */
s->dispc.irqst &= ~value;
omap_dispc_interrupt_update(s);
break;
case 0x01c: /* DISPC_IRQENABLE */
case 0x01c: /* DISPC_IRQENABLE */
s->dispc.irqen = value & 0xffff;
omap_dispc_interrupt_update(s);
break;
case 0x040: /* DISPC_CONTROL */
case 0x040: /* DISPC_CONTROL */
s->dispc.control = value & 0x07ff9fff;
s->dig.enable = (value >> 1) & 1;
s->lcd.enable = (value >> 0) & 1;
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
if (!((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) {
fprintf(stderr, "%s: Overlay Optimization when no overlay "
"region effectively exists leads to "
"unpredictable behaviour!\n", __func__);
}
if (value & (1 << 6)) { /* GODIGITAL */
if (value & (1 << 6)) { /* GODIGITAL */
/* XXX: Shadowed fields are:
* s->dispc.config
* s->dispc.capable
@ -444,13 +444,13 @@ static void omap_disc_write(void *opaque, hwaddr addr,
* All they need to be loaded here from their shadow registers.
*/
}
if (value & (1 << 5)) { /* GOLCD */
if (value & (1 << 5)) { /* GOLCD */
/* XXX: Likewise for LCD here. */
}
s->dispc.invalidate = 1;
break;
case 0x044: /* DISPC_CONFIG */
case 0x044: /* DISPC_CONFIG */
s->dispc.config = value & 0x3fff;
/* XXX:
* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
@ -459,73 +459,73 @@ static void omap_disc_write(void *opaque, hwaddr addr,
s->dispc.invalidate = 1;
break;
case 0x048: /* DISPC_CAPABLE */
case 0x048: /* DISPC_CAPABLE */
s->dispc.capable = value & 0x3ff;
break;
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
s->dispc.bg[0] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x050: /* DISPC_DEFAULT_COLOR1 */
case 0x050: /* DISPC_DEFAULT_COLOR1 */
s->dispc.bg[1] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x054: /* DISPC_TRANS_COLOR0 */
case 0x054: /* DISPC_TRANS_COLOR0 */
s->dispc.trans[0] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x058: /* DISPC_TRANS_COLOR1 */
case 0x058: /* DISPC_TRANS_COLOR1 */
s->dispc.trans[1] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x060: /* DISPC_LINE_NUMBER */
case 0x060: /* DISPC_LINE_NUMBER */
s->dispc.line = value & 0x7ff;
break;
case 0x064: /* DISPC_TIMING_H */
case 0x064: /* DISPC_TIMING_H */
s->dispc.timing[0] = value & 0x0ff0ff3f;
break;
case 0x068: /* DISPC_TIMING_V */
case 0x068: /* DISPC_TIMING_V */
s->dispc.timing[1] = value & 0x0ff0ff3f;
break;
case 0x06c: /* DISPC_POL_FREQ */
case 0x06c: /* DISPC_POL_FREQ */
s->dispc.timing[2] = value & 0x0003ffff;
break;
case 0x070: /* DISPC_DIVISOR */
case 0x070: /* DISPC_DIVISOR */
s->dispc.timing[3] = value & 0x00ff00ff;
break;
case 0x078: /* DISPC_SIZE_DIG */
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
case 0x078: /* DISPC_SIZE_DIG */
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
s->dispc.invalidate = 1;
break;
case 0x07c: /* DISPC_SIZE_LCD */
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
case 0x07c: /* DISPC_SIZE_LCD */
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
case 0x080: /* DISPC_GFX_BA0 */
s->dispc.l[0].addr[0] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
case 0x084: /* DISPC_GFX_BA1 */
s->dispc.l[0].addr[1] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
case 0x088: /* DISPC_GFX_POSITION */
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
s->dispc.invalidate = 1;
break;
case 0x08c: /* DISPC_GFX_SIZE */
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
case 0x08c: /* DISPC_GFX_SIZE */
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
s->dispc.invalidate = 1;
break;
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
s->dispc.l[0].attr = value & 0x7ff;
if (value & (3 << 9))
fprintf(stderr, "%s: Big-endian pixel format not supported\n",
@ -534,54 +534,54 @@ static void omap_disc_write(void *opaque, hwaddr addr,
s->dispc.l[0].bpp = (value >> 1) & 0xf;
s->dispc.invalidate = 1;
break;
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
s->dispc.l[0].tresh = value & 0x01ff01ff;
break;
case 0x0ac: /* DISPC_GFX_ROW_INC */
case 0x0ac: /* DISPC_GFX_ROW_INC */
s->dispc.l[0].rowinc = value;
s->dispc.invalidate = 1;
break;
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
s->dispc.l[0].colinc = value;
s->dispc.invalidate = 1;
break;
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
case 0x0b8: /* DISPC_GFX_TABLE_BA */
s->dispc.l[0].addr[2] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
break;
default:
@ -617,14 +617,14 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
if (!s->rfbi.enable || s->rfbi.busy)
return;
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
/* TODO: in non-Bypass mode we probably need to just assert the
* DRQ and wait for DMA to write the pixels. */
qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
return;
}
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
return;
/* TODO: check that LCD output is enabled in DISPC. */
@ -665,7 +665,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_rfbi_transfer_stop(s);
/* TODO */
s->dispc.irqst |= 1; /* FRAMEDONE */
s->dispc.irqst |= 1; /* FRAMEDONE */
omap_dispc_interrupt_update(s);
}
@ -679,57 +679,57 @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* RFBI_REVISION */
case 0x00: /* RFBI_REVISION */
return 0x10;
case 0x10: /* RFBI_SYSCONFIG */
case 0x10: /* RFBI_SYSCONFIG */
return s->rfbi.idlemode;
case 0x14: /* RFBI_SYSSTATUS */
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
case 0x14: /* RFBI_SYSSTATUS */
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
case 0x40: /* RFBI_CONTROL */
case 0x40: /* RFBI_CONTROL */
return s->rfbi.control;
case 0x44: /* RFBI_PIXELCNT */
case 0x44: /* RFBI_PIXELCNT */
return s->rfbi.pixels;
case 0x48: /* RFBI_LINE_NUMBER */
case 0x48: /* RFBI_LINE_NUMBER */
return s->rfbi.skiplines;
case 0x58: /* RFBI_READ */
case 0x5c: /* RFBI_STATUS */
case 0x58: /* RFBI_READ */
case 0x5c: /* RFBI_STATUS */
return s->rfbi.rxbuf;
case 0x60: /* RFBI_CONFIG0 */
case 0x60: /* RFBI_CONFIG0 */
return s->rfbi.config[0];
case 0x64: /* RFBI_ONOFF_TIME0 */
case 0x64: /* RFBI_ONOFF_TIME0 */
return s->rfbi.time[0];
case 0x68: /* RFBI_CYCLE_TIME0 */
case 0x68: /* RFBI_CYCLE_TIME0 */
return s->rfbi.time[1];
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
return s->rfbi.data[0];
case 0x70: /* RFBI_DATA_CYCLE2_0 */
case 0x70: /* RFBI_DATA_CYCLE2_0 */
return s->rfbi.data[1];
case 0x74: /* RFBI_DATA_CYCLE3_0 */
case 0x74: /* RFBI_DATA_CYCLE3_0 */
return s->rfbi.data[2];
case 0x78: /* RFBI_CONFIG1 */
case 0x78: /* RFBI_CONFIG1 */
return s->rfbi.config[1];
case 0x7c: /* RFBI_ONOFF_TIME1 */
case 0x7c: /* RFBI_ONOFF_TIME1 */
return s->rfbi.time[2];
case 0x80: /* RFBI_CYCLE_TIME1 */
case 0x80: /* RFBI_CYCLE_TIME1 */
return s->rfbi.time[3];
case 0x84: /* RFBI_DATA_CYCLE1_1 */
case 0x84: /* RFBI_DATA_CYCLE1_1 */
return s->rfbi.data[3];
case 0x88: /* RFBI_DATA_CYCLE2_1 */
case 0x88: /* RFBI_DATA_CYCLE2_1 */
return s->rfbi.data[4];
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
return s->rfbi.data[5];
case 0x90: /* RFBI_VSYNC_WIDTH */
case 0x90: /* RFBI_VSYNC_WIDTH */
return s->rfbi.vsync;
case 0x94: /* RFBI_HSYNC_WIDTH */
case 0x94: /* RFBI_HSYNC_WIDTH */
return s->rfbi.hsync;
}
OMAP_BAD_REG(addr);
@ -747,41 +747,41 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_rfbi_reset(s);
s->rfbi.idlemode = value & 0x19;
break;
case 0x40: /* RFBI_CONTROL */
case 0x40: /* RFBI_CONTROL */
s->rfbi.control = value & 0xf;
s->rfbi.enable = value & 1;
if (value & (1 << 4) && /* ITE */
if (value & (1 << 4) && /* ITE */
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc))
omap_rfbi_transfer_start(s);
break;
case 0x44: /* RFBI_PIXELCNT */
case 0x44: /* RFBI_PIXELCNT */
s->rfbi.pixels = value;
break;
case 0x48: /* RFBI_LINE_NUMBER */
case 0x48: /* RFBI_LINE_NUMBER */
s->rfbi.skiplines = value & 0x7ff;
break;
case 0x4c: /* RFBI_CMD */
case 0x4c: /* RFBI_CMD */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
break;
case 0x50: /* RFBI_PARAM */
case 0x50: /* RFBI_PARAM */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
break;
case 0x54: /* RFBI_DATA */
case 0x54: /* RFBI_DATA */
/* TODO: take into account the format set up in s->rfbi.config[?] and
* s->rfbi.data[?], but special-case the most usual scenario so that
* speed doesn't suffer. */
@ -796,7 +796,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
if (!-- s->rfbi.pixels)
omap_rfbi_transfer_stop(s);
break;
case 0x58: /* RFBI_READ */
case 0x58: /* RFBI_READ */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
@ -805,7 +805,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
omap_rfbi_transfer_stop(s);
break;
case 0x5c: /* RFBI_STATUS */
case 0x5c: /* RFBI_STATUS */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
@ -814,49 +814,49 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
omap_rfbi_transfer_stop(s);
break;
case 0x60: /* RFBI_CONFIG0 */
case 0x60: /* RFBI_CONFIG0 */
s->rfbi.config[0] = value & 0x003f1fff;
break;
case 0x64: /* RFBI_ONOFF_TIME0 */
case 0x64: /* RFBI_ONOFF_TIME0 */
s->rfbi.time[0] = value & 0x3fffffff;
break;
case 0x68: /* RFBI_CYCLE_TIME0 */
case 0x68: /* RFBI_CYCLE_TIME0 */
s->rfbi.time[1] = value & 0x0fffffff;
break;
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
s->rfbi.data[0] = value & 0x0f1f0f1f;
break;
case 0x70: /* RFBI_DATA_CYCLE2_0 */
case 0x70: /* RFBI_DATA_CYCLE2_0 */
s->rfbi.data[1] = value & 0x0f1f0f1f;
break;
case 0x74: /* RFBI_DATA_CYCLE3_0 */
case 0x74: /* RFBI_DATA_CYCLE3_0 */
s->rfbi.data[2] = value & 0x0f1f0f1f;
break;
case 0x78: /* RFBI_CONFIG1 */
case 0x78: /* RFBI_CONFIG1 */
s->rfbi.config[1] = value & 0x003f1fff;
break;
case 0x7c: /* RFBI_ONOFF_TIME1 */
case 0x7c: /* RFBI_ONOFF_TIME1 */
s->rfbi.time[2] = value & 0x3fffffff;
break;
case 0x80: /* RFBI_CYCLE_TIME1 */
case 0x80: /* RFBI_CYCLE_TIME1 */
s->rfbi.time[3] = value & 0x0fffffff;
break;
case 0x84: /* RFBI_DATA_CYCLE1_1 */
case 0x84: /* RFBI_DATA_CYCLE1_1 */
s->rfbi.data[3] = value & 0x0f1f0f1f;
break;
case 0x88: /* RFBI_DATA_CYCLE2_1 */
case 0x88: /* RFBI_DATA_CYCLE2_1 */
s->rfbi.data[4] = value & 0x0f1f0f1f;
break;
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
s->rfbi.data[5] = value & 0x0f1f0f1f;
break;
case 0x90: /* RFBI_VSYNC_WIDTH */
case 0x90: /* RFBI_VSYNC_WIDTH */
s->rfbi.vsync = value & 0xffff;
break;
case 0x94: /* RFBI_HSYNC_WIDTH */
case 0x94: /* RFBI_HSYNC_WIDTH */
s->rfbi.hsync = value & 0xffff;
break;
@ -879,49 +879,49 @@ static uint64_t omap_venc_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
return 0;
default:
@ -940,47 +940,47 @@ static void omap_venc_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
break;
default:
@ -1002,15 +1002,15 @@ static uint64_t omap_im3_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x1f8: /* SBID_L */
case 0x1fc: /* SBID_H */
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x1f8: /* SBID_L */
case 0x1fc: /* SBID_H */
return 0;
default:
@ -1029,12 +1029,12 @@ static void omap_im3_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
break;
default:

184
hw/display/pxa2xx_lcd.c
View File

@ -86,106 +86,106 @@ typedef struct QEMU_PACKED {
uint32_t ldcmd;
} PXAFrameDescriptor;
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
/* LCD Buffer Strength Control register */
#define BSCNTR 0x04000054
#define BSCNTR 0x04000054
/* Bitfield masks */
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
/* Size of a pixel in the QEMU UI output surface, in bytes */
#define DEST_PIXEL_WIDTH 4
@ -788,7 +788,7 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
case TCR:
return s->tcr;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;
@ -938,7 +938,7 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
s->tcr = value & 0x7fff;
break;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;

6
hw/display/vga_regs.h
View File

@ -4,9 +4,9 @@
* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
*
* Copyright history from vga16fb.c:
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this

258
hw/display/xenfb.c
View File

@ -76,7 +76,7 @@ struct XenFB {
int do_resize;
struct {
int x,y,w,h;
int x,y,w,h;
} up_rects[UP_QUEUE];
int up_count;
int up_fullscreen;
@ -116,32 +116,32 @@ static void common_unbind(struct common *c)
xen_pv_unbind_evtchn(&c->xendev);
if (c->page) {
xenforeignmemory_unmap(xen_fmem, c->page, 1);
c->page = NULL;
c->page = NULL;
}
}
/* -------------------------------------------------------------------- */
/* Send an event to the keyboard frontend driver */
static int xenfb_kbd_event(struct XenInput *xenfb,
union xenkbd_in_event *event)
union xenkbd_in_event *event)
{
struct xenkbd_page *page = xenfb->c.page;
uint32_t prod;
if (xenfb->c.xendev.be_state != XenbusStateConnected)
return 0;
return 0;
if (!page)
return 0;
prod = page->in_prod;
if (prod - page->in_cons == XENKBD_IN_RING_LEN) {
errno = EAGAIN;
return -1;
errno = EAGAIN;
return -1;
}
xen_mb(); /* ensure ring space available */
xen_mb(); /* ensure ring space available */
XENKBD_IN_RING_REF(page, prod) = *event;
xen_wmb(); /* ensure ring contents visible */
xen_wmb(); /* ensure ring contents visible */
page->in_prod = prod + 1;
return xen_pv_send_notify(&xenfb->c.xendev);
}
@ -161,7 +161,7 @@ static int xenfb_send_key(struct XenInput *xenfb, bool down, int keycode)
/* Send a relative mouse movement event */
static int xenfb_send_motion(struct XenInput *xenfb,
int rel_x, int rel_y, int rel_z)
int rel_x, int rel_y, int rel_z)
{
union xenkbd_in_event event;
@ -176,7 +176,7 @@ static int xenfb_send_motion(struct XenInput *xenfb,
/* Send an absolute mouse movement event */
static int xenfb_send_position(struct XenInput *xenfb,
int abs_x, int abs_y, int z)
int abs_x, int abs_y, int z)
{
union xenkbd_in_event event;
@ -354,7 +354,7 @@ static int input_initialise(struct XenLegacyDevice *xendev)
rc = common_bind(&in->c);
if (rc != 0)
return rc;
return rc;
return 0;
}
@ -415,7 +415,7 @@ static void input_event(struct XenLegacyDevice *xendev)
/* We don't understand any keyboard events, so just ignore them. */
if (page->out_prod == page->out_cons)
return;
return;
page->out_cons = page->out_prod;
xen_pv_send_notify(&xenfb->c.xendev);
}
@ -429,7 +429,7 @@ static void xenfb_copy_mfns(int mode, int count, xen_pfn_t *dst, void *src)
int i;
for (i = 0; i < count; i++)
dst[i] = (mode == 32) ? src32[i] : src64[i];
dst[i] = (mode == 32) ? src32[i] : src64[i];
}
static int xenfb_map_fb(struct XenFB *xenfb)
@ -447,43 +447,43 @@ static int xenfb_map_fb(struct XenFB *xenfb)
mode = sizeof(unsigned long) * 8;
if (!protocol) {
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
#if defined(__i386__)
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
#elif defined(__x86_64__)
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
#endif
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
#if defined(__x86_64__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_32) == 0) {
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
#elif defined(__i386__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_64) == 0) {
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
#endif
}
@ -503,14 +503,14 @@ static int xenfb_map_fb(struct XenFB *xenfb)
map = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, n_fbdirs, pgmfns, NULL);
if (map == NULL)
goto out;
goto out;
xenfb_copy_mfns(mode, xenfb->fbpages, fbmfns, map);
xenforeignmemory_unmap(xen_fmem, map, n_fbdirs);
xenfb->pixels = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, xenfb->fbpages, fbmfns, NULL);
if (xenfb->pixels == NULL)
goto out;
goto out;
ret = 0; /* all is fine */
@ -589,35 +589,35 @@ static int xenfb_configure_fb(struct XenFB *xenfb, size_t fb_len_lim,
/* A convenient function for munging pixels between different depths */
#define BLT(SRC_T,DST_T,RSB,GSB,BSB,RDB,GDB,BDB) \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
}
@ -657,7 +657,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h)
break;
default:
oops = 1;
}
}
}
if (oops) /* should not happen */
xen_pv_printf(&xenfb->c.xendev, 0, "%s: oops: convert %d -> %d bpp?\n",
@ -816,60 +816,60 @@ static void xenfb_handle_events(struct XenFB *xenfb)
if (prod - out_cons > XENFB_OUT_RING_LEN) {
return;
}
xen_rmb(); /* ensure we see ring contents up to prod */
xen_rmb(); /* ensure we see ring contents up to prod */
for (cons = out_cons; cons != prod; cons++) {
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
uint8_t type = event->type;
int x, y, w, h;
int x, y, w, h;
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update ignored\n");
break;
}
if (x != event->update.x ||
break;
}
if (x != event->update.x ||
y != event->update.y ||
w != event->update.width ||
h != event->update.height) {
w != event->update.width ||
h != event->update.height) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update clipped\n");
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
#ifdef XENFB_TYPE_RESIZE
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
#endif
}
}
}
xen_mb(); /* ensure we're done with ring contents */
xen_mb(); /* ensure we're done with ring contents */
page->out_cons = cons;
}
@ -889,32 +889,32 @@ static int fb_initialise(struct XenLegacyDevice *xendev)
int rc;
if (xenstore_read_fe_int(xendev, "videoram", &videoram) == -1)
videoram = 0;
videoram = 0;
rc = common_bind(&fb->c);
if (rc != 0)
return rc;
return rc;
fb_page = fb->c.page;
rc = xenfb_configure_fb(fb, videoram * MiB,
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
if (rc != 0)
return rc;
return rc;
rc = xenfb_map_fb(fb);
if (rc != 0)
return rc;
return rc;
fb->con = graphic_console_init(NULL, 0, &xenfb_ops, fb);
if (xenstore_read_fe_int(xendev, "feature-update", &fb->feature_update) == -1)
fb->feature_update = 0;
fb->feature_update = 0;
if (fb->feature_update)
xenstore_write_be_int(xendev, "request-update", 1);
xenstore_write_be_int(xendev, "request-update", 1);
xen_pv_printf(xendev, 1, "feature-update=%d, videoram=%d\n",
fb->feature_update, videoram);
fb->feature_update, videoram);
return 0;
}