diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 56d60e9ac9..af4ae3630e 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -454,10 +454,10 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 
     for (i = 0; i < plic->num_addrs; i++) {
         int cpu_num = plic->addr_config[i].hartid;
-        CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num);
+        CPUState *cpu = qemu_get_cpu(cpu_num);
 
         if (plic->addr_config[i].mode == PLICMode_M) {
-            qdev_connect_gpio_out(dev, num_harts + cpu_num,
+            qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
         }
         if (plic->addr_config[i].mode == PLICMode_S) {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bb3973806..ac6f82ebd0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_ifencei = true;
         }
 
-        if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
-            warn_report("Zmmul will override M");
-            cpu->cfg.ext_m = false;
-        }
-
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
                        "I and E extensions are incompatible");