From 44602af8585fd2f331c69e2c071eff39227535ed Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Thu, 14 Jul 2022 11:00:33 -0700 Subject: [PATCH 1/2] RISC-V: Allow both Zmmul and M We got to talking about how Zmmul and M interact with each other https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out that QEMU's behavior is slightly wrong: having Zmmul and M is a legal combination, it just means that the multiplication instructions are supported even when M is disabled at runtime via misa. This just stops overriding M from Zmmul, with that the other checks for the multiplication instructions work as per the ISA. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <20220714180033.22385-1-palmer@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..ac6f82ebd0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -619,11 +619,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } - if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) { - warn_report("Zmmul will override M"); - cpu->cfg.ext_m = false; - } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); From 54f218363052be210e77d2ada8c0c1e51b3ad6cd Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Sat, 23 Jul 2022 02:03:35 -0700 Subject: [PATCH 2/2] hw/intc: sifive_plic: Fix multi-socket plic configuraiton Since commit 40244040a7ac, multi-socket configuration with plic is broken as the hartid for second socket is calculated incorrectly. The hartid stored in addr_config already includes the offset for the base hartid for that socket. Adding it again would lead to segfault while creating the plic device for the virt machine. qdev_connect_gpio_out was also invoked with incorrect number of gpio lines. Fixes: 40244040a7ac (hw/intc: sifive_plic: Avoid overflowing the addr_config buffer) Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Message-Id: <20220723090335.671105-1-atishp@rivosinc.com> [ Changes by AF: - Change the qdev_connect_gpio_out() numbering ] Signed-off-by: Alistair Francis --- hw/intc/sifive_plic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 56d60e9ac9..af4ae3630e 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -454,10 +454,10 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, for (i = 0; i < plic->num_addrs; i++) { int cpu_num = plic->addr_config[i].hartid; - CPUState *cpu = qemu_get_cpu(hartid_base + cpu_num); + CPUState *cpu = qemu_get_cpu(cpu_num); if (plic->addr_config[i].mode == PLICMode_M) { - qdev_connect_gpio_out(dev, num_harts + cpu_num, + qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); } if (plic->addr_config[i].mode == PLICMode_S) {