xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-23 19:49:43 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

PPC: e500: Map PIO space into core memory region

Browse Source 
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
accessible via MMIO. Do this mapping explicitly by mapping the PIO space
of our PCI bus into a memory region that lives in memory space.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2012-10-08 12:21:30 +02:00
parent 626c7a171e
commit a1bc20dfbb
2 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/ppc/e500.c
View File

@ -52,7 +52,6 @@
#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL) #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL)
#define MPC8544_PCI_REGS_SIZE 0x1000ULL #define MPC8544_PCI_REGS_SIZE 0x1000ULL
#define MPC8544_PCI_IO 0xE1000000ULL #define MPC8544_PCI_IO 0xE1000000ULL
#define MPC8544_PCI_IOLEN 0x10000ULL
#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL) #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
#define MPC8544_SPIN_BASE 0xEF000000ULL #define MPC8544_SPIN_BASE 0xEF000000ULL
@ -511,7 +510,7 @@ void ppce500_init(PPCE500Params *params)
if (!pci_bus) if (!pci_bus)
printf("couldn't create PCI controller!\n"); printf("couldn't create PCI controller!\n");
isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
if (pci_bus) { if (pci_bus) {
/* Register network interfaces. */ /* Register network interfaces. */

9
hw/ppce500_pci.c
View File

@ -31,6 +31,8 @@
#define PCIE500_ALL_SIZE 0x1000 #define PCIE500_ALL_SIZE 0x1000
#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
#define PCIE500_PCI_IOLEN 0x10000ULL
#define PPCE500_PCI_CONFIG_ADDR 0x0 #define PPCE500_PCI_CONFIG_ADDR 0x0
#define PPCE500_PCI_CONFIG_DATA 0x4 #define PPCE500_PCI_CONFIG_DATA 0x4
#define PPCE500_PCI_INTACK 0x8 #define PPCE500_PCI_INTACK 0x8
@ -87,6 +89,7 @@ struct PPCE500PCIState {
/* mmio maps */ /* mmio maps */
MemoryRegion container; MemoryRegion container;
MemoryRegion iomem; MemoryRegion iomem;
MemoryRegion pio;
}; };
typedef struct PPCE500PCIState PPCE500PCIState; typedef struct PPCE500PCIState PPCE500PCIState;
@ -314,7 +317,6 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
PCIBus *b; PCIBus *b;
int i; int i;
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *address_space_io = get_system_io();
h = PCI_HOST_BRIDGE(dev); h = PCI_HOST_BRIDGE(dev);
s = PPC_E500_PCI_HOST_BRIDGE(dev); s = PPC_E500_PCI_HOST_BRIDGE(dev);
@ -323,9 +325,11 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq[i]); sysbus_init_irq(dev, &s->irq[i]);
} }
memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
mpc85xx_pci_map_irq, s->irq, address_space_mem, mpc85xx_pci_map_irq, s->irq, address_space_mem,
address_space_io, PCI_DEVFN(0x11, 0), 4); &s->pio, PCI_DEVFN(0x11, 0), 4);
h->bus = b; h->bus = b;
pci_create_simple(b, 0, "e500-host-bridge"); pci_create_simple(b, 0, "e500-host-bridge");
@ -341,6 +345,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
sysbus_init_mmio(dev, &s->container); sysbus_init_mmio(dev, &s->container);
sysbus_init_mmio(dev, &s->pio);
return 0; return 0;
} }