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pull-loongarch-20221017

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Merge tag 'pull-loongarch-20221017' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20221017

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* tag 'pull-loongarch-20221017' of https://gitlab.com/gaosong/qemu:
  hw/intc: Fix LoongArch ipi device emulation
  linux-user: Fix struct statfs ABI on loongarch64
  softfloat: logB(0) should raise divideByZero exception
  target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
  target/loongarch: bstrins.w src register need EXT_NONE

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2022-10-17 13:40:56 -04:00
commit a1bf4f8904
5 changed files with 33 additions and 24 deletions
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1
fpu/softfloat-parts.c.inc
View File

@ -1436,6 +1436,7 @@ static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt)
parts_return_nan(a, s);
return;
case float_class_zero:
float_raise(float_flag_divbyzero, s);
/* log2(0) = -inf */
a->cls = float_class_inf;
a->sign = 1;

1
hw/intc/loongarch_ipi.c
View File

@ -88,7 +88,6 @@ static void ipi_send(uint64_t val)
cs = qemu_get_cpu(cpuid);
cpu = LOONGARCH_CPU(cs);
env = &cpu->env;
loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);
address_space_stl(&env->address_space_iocsr, 0x1008,
data, MEMTXATTRS_UNSPECIFIED, NULL);

3
linux-user/syscall_defs.h
View File

@ -2262,7 +2262,8 @@ struct target_statfs64 {
};
#elif (defined(TARGET_PPC64) || defined(TARGET_X86_64) || \
defined(TARGET_SPARC64) || defined(TARGET_AARCH64) || \
defined(TARGET_RISCV)) && !defined(TARGET_ABI32)
defined(TARGET_RISCV) || defined(TARGET_LOONGARCH64)) && \
!defined(TARGET_ABI32)
struct target_statfs {
abi_long f_type;
abi_long f_bsize;

40
target/loongarch/insn_trans/trans_bit.c.inc
View File

@ -27,26 +27,34 @@ static void gen_bytepick_d(TCGv dest, TCGv src1, TCGv src2, target_long sa)
tcg_gen_extract2_i64(dest, src1, src2, (64 - sa * 8));
}
static void gen_bstrins(TCGv dest, TCGv src1,
unsigned int ls, unsigned int len)
static bool gen_bstrins(DisasContext *ctx, arg_rr_ms_ls *a,
DisasExtend dst_ext)
{
tcg_gen_deposit_tl(dest, dest, src1, ls, len);
}
static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
DisasExtend src_ext, DisasExtend dst_ext,
void (*func)(TCGv, TCGv, unsigned int, unsigned int))
{
TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
TCGv src1 = gpr_src(ctx, a->rj, src_ext);
TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
if (a->ls > a->ms) {
return false;
}
func(dest, src1, a->ls, a->ms - a->ls + 1);
tcg_gen_deposit_tl(dest, src1, src2, a->ls, a->ms - a->ls + 1);
gen_set_gpr(a->rd, dest, dst_ext);
return true;
}
static bool gen_bstrpick(DisasContext *ctx, arg_rr_ms_ls *a,
DisasExtend dst_ext)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
if (a->ls > a->ms) {
return false;
}
tcg_gen_extract_tl(dest, src1, a->ls, a->ms - a->ls + 1);
gen_set_gpr(a->rd, dest, dst_ext);
return true;
}
@ -206,7 +214,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
TRANS(bstrins_d, gen_bstrins, EXT_NONE)
TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)

12
target/loongarch/insn_trans/trans_farith.c.inc
View File

@ -97,9 +97,9 @@ TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,
float_muladd_negate_product | float_muladd_negate_c)
TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,
float_muladd_negate_product | float_muladd_negate_c)
TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)
TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)
TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
float_muladd_negate_c | float_muladd_negate_result)
TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
float_muladd_negate_c | float_muladd_negate_result)