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pci_host: consolidate pci config address access.
consolidate pci_config address access into pci_host.c Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Isaku Yamahata
Anthony Liguori
parent
4f5e19e6c5
commit
a455783bb6
43
hw/apb_pci.c
43
hw/apb_pci.c
@ -54,46 +54,6 @@ typedef struct APBState {
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PCIHostState host_state;
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} APBState;
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static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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APBState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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s->host_state.config_reg = val;
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}
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static uint32_t pci_apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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APBState *s = opaque;
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uint32_t val;
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val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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};
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static CPUReadMemoryFunc * const pci_apb_config_read[] = {
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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};
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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@ -275,8 +235,7 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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pci_apb_iowrite, s);
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
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/* mem_config */
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pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
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pci_apb_config_write, s);
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pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
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sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
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/* mem_data */
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pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
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@ -43,45 +43,6 @@ typedef struct GrackleState {
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PCIHostState host_state;
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} GrackleState;
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static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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GrackleState *s = opaque;
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GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->host_state.config_reg = val;
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}
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static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
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{
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GrackleState *s = opaque;
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uint32_t val;
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val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
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&pci_grackle_config_writel,
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&pci_grackle_config_writel,
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&pci_grackle_config_writel,
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};
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static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
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&pci_grackle_config_readl,
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&pci_grackle_config_readl,
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&pci_grackle_config_readl,
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};
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/* Don't know if this matches real hardware, but it agrees with OHW. */
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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@ -147,8 +108,7 @@ static int pci_grackle_init_device(SysBusDevice *dev)
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s = FROM_SYSBUS(GrackleState, dev);
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pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
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pci_grackle_config_write, s);
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pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
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pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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@ -166,8 +126,7 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
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s = FROM_SYSBUS(GrackleState, dev);
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pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
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pci_grackle_config_write, s);
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pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
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pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
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sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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108
hw/pci_host.c
108
hw/pci_host.c
@ -32,6 +32,114 @@ do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
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#define PCI_DPRINTF(fmt, ...)
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#endif
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static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIHostState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val);
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s->config_reg = val;
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}
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static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr)
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{
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PCIHostState *s = opaque;
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uint32_t val = s->config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_host_config_write[] = {
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&pci_host_config_writel,
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&pci_host_config_writel,
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&pci_host_config_writel,
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};
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static CPUReadMemoryFunc * const pci_host_config_read[] = {
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&pci_host_config_readl,
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&pci_host_config_readl,
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&pci_host_config_readl,
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};
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int pci_host_config_register_io_memory(PCIHostState *s)
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{
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return cpu_register_io_memory(pci_host_config_read,
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pci_host_config_write, s);
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}
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static void pci_host_config_writel_noswap(void *opaque,
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target_phys_addr_t addr,
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uint32_t val)
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{
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PCIHostState *s = opaque;
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val);
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s->config_reg = val;
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}
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static uint32_t pci_host_config_readl_noswap(void *opaque,
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target_phys_addr_t addr)
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{
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PCIHostState *s = opaque;
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uint32_t val = s->config_reg;
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
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&pci_host_config_writel_noswap,
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&pci_host_config_writel_noswap,
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&pci_host_config_writel_noswap,
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};
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static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
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&pci_host_config_readl_noswap,
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&pci_host_config_readl_noswap,
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&pci_host_config_readl_noswap,
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};
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int pci_host_config_register_io_memory_noswap(PCIHostState *s)
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{
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return cpu_register_io_memory(pci_host_config_read_noswap,
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pci_host_config_write_noswap, s);
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}
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static void pci_host_config_writel_ioport(void *opaque,
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uint32_t addr, uint32_t val)
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{
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PCIHostState *s = opaque;
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PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
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s->config_reg = val;
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}
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static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
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{
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PCIHostState *s = opaque;
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uint32_t val = s->config_reg;
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PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
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return val;
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}
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void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s)
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{
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register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
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register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
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}
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#define PCI_ADDR_T target_phys_addr_t
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#define PCI_HOST_SUFFIX _mmio
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@ -37,9 +37,12 @@ typedef struct {
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} PCIHostState;
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/* for mmio */
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int pci_host_config_register_io_memory(PCIHostState *s);
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int pci_host_config_register_io_memory_noswap(PCIHostState *s);
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int pci_host_data_register_io_memory(PCIHostState *s);
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/* for ioio */
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void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s);
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void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
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#endif /* PCI_HOST_H */
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@ -44,18 +44,6 @@ struct PCII440FXState {
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PIIX3State *piix3;
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};
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static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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I440FXState *s = opaque;
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s->config_reg = val;
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}
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static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
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{
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I440FXState *s = opaque;
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return s->config_reg;
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}
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static void piix3_set_irq(void *opaque, int irq_num, int level);
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/* return the global irq number corresponding to a given device irq
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@ -192,8 +180,7 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
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{
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I440FXState *s = FROM_SYSBUS(I440FXState, dev);
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register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
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pci_host_config_register_ioport(0xcf8, s);
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pci_host_data_register_ioport(0xcfc, s);
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return 0;
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@ -84,37 +84,6 @@ struct PPCE500PCIState {
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typedef struct PPCE500PCIState PPCE500PCIState;
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static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
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{
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PPCE500PCIState *pci = opaque;
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pci_debug("%s: (addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, addr,
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pci->pci_state.config_reg);
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return pci->pci_state.config_reg;
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}
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static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = {
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&pcie500_cfgaddr_readl,
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&pcie500_cfgaddr_readl,
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&pcie500_cfgaddr_readl,
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};
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static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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PPCE500PCIState *controller = opaque;
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pci_debug("%s: value:%x -> (addr:" TARGET_FMT_plx ")\n", __func__, value,
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addr);
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controller->pci_state.config_reg = value & ~0x3;
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}
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static CPUWriteMemoryFunc * const pcie500_cfgaddr_write[] = {
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&pcie500_cfgaddr_writel,
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&pcie500_cfgaddr_writel,
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&pcie500_cfgaddr_writel,
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};
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static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
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{
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PPCE500PCIState *pci = opaque;
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@ -324,8 +293,7 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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controller->pci_dev = d;
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/* CFGADDR */
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index = cpu_register_io_memory(pcie500_cfgaddr_read,
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pcie500_cfgaddr_write, controller);
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index = pci_host_config_register_io_memory_noswap(&controller->pci_state);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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@ -28,18 +28,6 @@
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typedef PCIHostState PREPPCIState;
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static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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PREPPCIState *s = opaque;
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s->config_reg = val;
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}
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static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
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{
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PREPPCIState *s = opaque;
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return s->config_reg;
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}
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static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
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{
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int i;
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@ -139,8 +127,7 @@ PCIBus *pci_prep_init(qemu_irq *pic)
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s->bus = pci_register_bus(NULL, "pci",
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prep_set_irq, prep_map_irq, pic, 0, 4);
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register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
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pci_host_config_register_ioport(0xcf8, s);
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pci_host_data_register_ioport(0xcfc, s);
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@ -41,74 +41,6 @@ typedef struct UNINState {
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PCIHostState host_state;
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} UNINState;
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static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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UNINState *s = opaque;
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UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->host_state.config_reg = val;
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}
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static uint32_t pci_unin_main_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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UNINState *s = opaque;
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uint32_t val;
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val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = {
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&pci_unin_main_config_writel,
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&pci_unin_main_config_writel,
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&pci_unin_main_config_writel,
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};
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static CPUReadMemoryFunc * const pci_unin_main_config_read[] = {
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&pci_unin_main_config_readl,
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&pci_unin_main_config_readl,
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&pci_unin_main_config_readl,
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};
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static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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UNINState *s = opaque;
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s->host_state.config_reg = val;
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}
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static uint32_t pci_unin_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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UNINState *s = opaque;
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return s->host_state.config_reg;
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}
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static CPUWriteMemoryFunc * const pci_unin_config_write[] = {
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&pci_unin_config_writel,
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&pci_unin_config_writel,
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&pci_unin_config_writel,
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};
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static CPUReadMemoryFunc * const pci_unin_config_read[] = {
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&pci_unin_config_readl,
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&pci_unin_config_readl,
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&pci_unin_config_readl,
|
||||
};
|
||||
|
||||
/* Don't know if this matches real hardware, but it agrees with OHW. */
|
||||
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
|
||||
{
|
||||
@ -152,10 +84,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
|
||||
/* Uninorth main bus */
|
||||
s = FROM_SYSBUS(UNINState, dev);
|
||||
|
||||
pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read,
|
||||
pci_unin_main_config_write, s);
|
||||
pci_mem_config = pci_host_config_register_io_memory(&s->host_state);
|
||||
pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
|
||||
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
|
||||
|
||||
@ -173,8 +103,7 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
|
||||
s = FROM_SYSBUS(UNINState, dev);
|
||||
|
||||
// XXX: s = &pci_bridge[2];
|
||||
pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
|
||||
pci_unin_config_write, s);
|
||||
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state);
|
||||
pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
|
||||
@ -189,8 +118,7 @@ static int pci_unin_agp_init_device(SysBusDevice *dev)
|
||||
/* Uninorth AGP bus */
|
||||
s = FROM_SYSBUS(UNINState, dev);
|
||||
|
||||
pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
|
||||
pci_unin_config_write, s);
|
||||
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state);
|
||||
pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
|
||||
@ -205,8 +133,7 @@ static int pci_unin_internal_init_device(SysBusDevice *dev)
|
||||
/* Uninorth internal bus */
|
||||
s = FROM_SYSBUS(UNINState, dev);
|
||||
|
||||
pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
|
||||
pci_unin_config_write, s);
|
||||
pci_mem_config = pci_host_config_register_io_memory_noswap(&s->host_state);
|
||||
pci_mem_data = pci_host_data_register_io_memory(&s->host_state);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
|
||||
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user