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target/arm: Define an aa32_pmu_8_1 isar feature test function
Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200214175116.9164-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
d52c061e54
commit
a617953855
@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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case 0xd44: /* PFR1. */
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return cpu->id_pfr1;
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case 0xd48: /* DFR0. */
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return cpu->id_dfr0;
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return cpu->isar.id_dfr0;
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case 0xd4c: /* AFR0. */
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return cpu->id_afr0;
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case 0xd50: /* MMFR0. */
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@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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#endif
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} else {
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cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
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cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
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cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
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cpu->pmceid0 = 0;
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cpu->pmceid1 = 0;
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}
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@ -1957,7 +1957,7 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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@ -1989,7 +1989,7 @@ static void arm1136_initfn(Object *obj)
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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@ -2022,7 +2022,7 @@ static void arm1176_initfn(Object *obj)
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x11;
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cpu->id_dfr0 = 0x33;
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cpu->isar.id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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@ -2052,7 +2052,7 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0;
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cpu->isar.id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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@ -2084,7 +2084,7 @@ static void cortex_m3_initfn(Object *obj)
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cpu->pmsav7_dregion = 8;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->id_dfr0 = 0x00100000;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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@ -2115,7 +2115,7 @@ static void cortex_m4_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000000;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->id_dfr0 = 0x00100000;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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@ -2146,7 +2146,7 @@ static void cortex_m7_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000040;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000200;
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cpu->id_dfr0 = 0x00100000;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00100030;
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cpu->id_mmfr1 = 0x00000000;
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@ -2179,7 +2179,7 @@ static void cortex_m33_initfn(Object *obj)
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cpu->isar.mvfr2 = 0x00000040;
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cpu->id_pfr0 = 0x00000030;
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cpu->id_pfr1 = 0x00000210;
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cpu->id_dfr0 = 0x00200000;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00101F40;
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cpu->id_mmfr1 = 0x00000000;
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@ -2231,7 +2231,7 @@ static void cortex_r5_initfn(Object *obj)
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cpu->midr = 0x411fc153; /* r1p3 */
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cpu->id_pfr0 = 0x0131;
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cpu->id_pfr1 = 0x001;
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cpu->id_dfr0 = 0x010400;
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cpu->isar.id_dfr0 = 0x010400;
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cpu->id_afr0 = 0x0;
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cpu->id_mmfr0 = 0x0210030;
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cpu->id_mmfr1 = 0x00000000;
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@ -2286,7 +2286,7 @@ static void cortex_a8_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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cpu->id_pfr1 = 0x11;
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cpu->id_dfr0 = 0x400;
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cpu->isar.id_dfr0 = 0x400;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x31100003;
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cpu->id_mmfr1 = 0x20000000;
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@ -2359,7 +2359,7 @@ static void cortex_a9_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x1031;
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cpu->id_pfr1 = 0x11;
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cpu->id_dfr0 = 0x000;
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cpu->isar.id_dfr0 = 0x000;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x00100103;
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cpu->id_mmfr1 = 0x20000000;
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@ -2424,7 +2424,7 @@ static void cortex_a7_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x02010555;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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@ -2470,7 +2470,7 @@ static void cortex_a15_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50078;
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x02010555;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x20000000;
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@ -865,6 +865,7 @@ struct ARMCPU {
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t mvfr2;
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uint32_t id_dfr0;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64pfr0;
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@ -880,7 +881,6 @@ struct ARMCPU {
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uint32_t reset_sctlr;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t id_dfr0;
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uint64_t pmceid0;
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uint64_t pmceid1;
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uint32_t id_afr0;
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@ -3500,6 +3500,13 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
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}
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static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
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{
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/* 0xf means "non-standard IMPDEF PMU" */
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return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
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FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
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}
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/*
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* 64-bit feature tests via id registers.
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*/
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@ -121,7 +121,7 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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@ -175,7 +175,7 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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@ -228,7 +228,7 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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@ -6381,8 +6381,7 @@ static void define_pmu_regs(ARMCPU *cpu)
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g_free(pmevtyper_name);
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g_free(pmevtyper_el0_name);
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}
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if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
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FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
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if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
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ARMCPRegInfo v81_pmu_regs[] = {
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{ .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
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@ -6856,7 +6855,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_dfr0 },
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.resetvalue = cpu->isar.id_dfr0 },
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{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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